SAB 82525 H V2.2 Infineon Technologies, SAB 82525 H V2.2 Datasheet - Page 71

• Manufacturer Part Number: SAB 82525 H V2.2
• Description: IC CONTROLLER HSCX MQFP-44
• Manufacturer: Infineon Technologies

Specifications of SAB 82525 H V2.2

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAB82525HV2.2X; SAB82525HV22XP; SP000063654

Table 9
User Demand Registers
User Demand
CTS/RFS Interrupt Provided
Selective Interrupts Should be Masked
Timer will be used by CPU (external timer mode)
DMA Controlled Data Transfer
Receive Length Check Feature
Extended (module 128) Counting
7.3 Operational Phase
After having performed the initialization, the CPU switches each individual channel of the
HSCX into operational phase by setting the PU bit in the CCR1 register (power-up, if not
already done during initialization).
Initially, the CPU should bring the transmitter and receiver to a defined state by issuing a XRES
(transmitter reset) and RHR (receiver reset) command via the CMDR register. If data reception
should be performed, the receiver must be activated by setting the RAC bit in MODE to 1.
If no "Clear to send" function is provided via a modem, the CTS pin of the HSCX must be
connected directly to ground, in order to enable data transmission.
Now the HSCX is ready to transmit and receive data. The control of the data transfer phase is
mainly done by commands from CPU to HSCX via the CMDR register, and by interrupt
indications from HSCX to CPU.
Additional status information, which does not trigger an interrupt, is available in the STAR
register.
7.4 Data Transmission
Interrupt Mode
In transmit direction 2 32 byte FIFO buffers (transmit pools) are provided for each channel.
After checking the XFIFO status by polling the Transmit FIFO Write Enable bit (XFW in STAR
register) or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes may be entered by the
CPU to the XFIFO.
The transmission of a frame can then be started issuing a XTF or XIF command via the CMDR
register. If the transmit command does not include an end of message indication
(CMDR : XME), the HSCX will repeatedly request for the next data block by means of a XPR
interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is
accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per command, after
which frame transmission is finished correctly by appending the CRC and closing flag
sequence.
In case no more data is available in the XFIFO prior to the arrival of XME, the transmission of
the frame is terminated with an abort sequence and the CPU is notified per interrupt
(EXIR : XDU). The frame may also be aborted per software (CMDR : XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in figure 32.
Semiconductor Group
71
Register
CCR2
MASK
TIMR
XBCH
RLCR
RAH2
SAB 82525
SAB 82526
SAF 82525
SAF 82526