SAB 82525 N V2.2 Infineon Technologies, SAB 82525 N V2.2 Datasheet - Page 34

• Manufacturer Part Number: SAB 82525 N V2.2
• Description: IC CONTROLLER HSCX PLCC-44
• Manufacturer: Infineon Technologies

Specifications of SAB 82525 N V2.2

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAB82525NV2.2XT; SAB82525NV22XK; SP000063649; SP000084997

3.2 Half-Duplex SDLC-NRM Operation
The LAP controllers of the two serial channels can be configured to function in a half-duplex
Normal Response Mode (NRM), where they will operate as a slave (secondary) station, by
setting the NRM bit in the XBCH register of the respective channel.
In contrast to the full-duplex LAPB/LAPD operation, where the combined (primary +
secondary) station transmits both commands and responses and may transmit data at any
time, the NRM mode allows only responses to be transmitted and the secondary station may
transmit only when instructed to do so by the master (primary) station.
The HSCX gets the permission to transmit a frame from the primary by an S-, or I-frame with
the poll bit (p) set!
The NRM mode can be profitably used in a point-to-multipoint configuration with a fixed
master-slave relationship and avoids collisions on the common transmit line. It’s the
responsibility of the master station to poll the slaves periodically and to process the error
recovery.
Prerequisite for NRM operation is:
Reception of Frames
The reception of frames functions equally to the LAPB/LAPD operation.
Transmission of Frames
The HSCX does not transmit S-, or I-frames if not instructed to do so by the primary station
sending an S-, or I-frame with the poll bit set.
The HSCX can be prepared to send an I-frame by the CPU issuing an XIF command (via
CMDR) at any time. The transmission of the frame, however, will not be initiated by the HSCX
prior to the reception of either a
with a poll bit set (p = 1).
After the frame has been transmitted (with the final bit set), the XFIFO is inhibited and the
HSCX waits for the arrival of a positive acknowledgement.
Semiconductor Group
Note: The broadcast address may be programmed in RAL2 if broadcasting is required.
MODE: TDM = 0
XAD1 = XAD2 = RAL1 = RAL2
MODE: MDS0, MDS1, ADM = 000
auto-mode with 8-bit address field selected
external timer mode
same transmit and receive addresses, since only responses can be transmitted, i.e.
RR, or
I-frame
(address of secondary)
34
SAB 82525
SAB 82526
SAF 82525
SAF 82526
901.90