AD9859YSVZ Analog Devices Inc, AD9859YSVZ Datasheet - Page 20

• Manufacturer Part Number: AD9859YSVZ
• Description: IC DDS DAC 10BIT 400MSPS 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9859YSVZ

• Resolution (bits): 10 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9859/PCB - BOARD EVAL FOR AD9859
• Lead Free Status / Rohs Status: Compliant

AD9859
There are two phases to a communication cycle with the
AD9859. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9859, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9859 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9859. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9859
and the system controller. The number of bytes transferred
SCLK
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDIO
SDO
CS
CS
CS
CS
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I
7
7
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I
7
7
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6
6
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6
6
INSTRUCTION CYCLE
Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High
INSTRUCTION CYCLE
I
INSTRUCTION CYCLE
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INSTRUCTION CYCLE
Figure 22. 3-Wire Serial Port Read Timing—Clock Stall Low
5
5
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5
5
Figure 23. Serial Port Write Timing—Clock Stall High
Figure 21. Serial Port Write Timing—Clock Stall Low
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4
4
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4
4
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3
3
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3
3
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2
2
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2
2
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I
1
1
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1
1
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0
0
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0
0
D
D
O 7
7
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, Phase 2 requires that four bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9859
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9859 is registered on the rising edge of
SCLK. All data is driven out of the AD9859 on the falling edge
of SCLK. Figure 21 through Figure 24 are useful in understand-
ing the general operation of the AD9859 serial port.
D
7
D
O 7
D
D
6
O 6
D
D
O 6
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
6
D
D
5
O 5
DON'T CARE
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O 5
5
D
D
4
O 4
D
D
O 4
4
D
D
3
O 3
D
D
O 3
D
3
D
2
O 2
D
D
O 2
2
D
D
1
O 1
D
D
O 1
1
D
0
D
O 0
D
O 0
D
0