ISL5314INZ Intersil, ISL5314INZ Datasheet - Page 16

• Manufacturer Part Number: ISL5314INZ
• Description: IC SYNTHESIZER DIGITAL 48-MQFP
• Manufacturer: Intersil

Specifications of ISL5314INZ

• Resolution (bits): 14 b
• Master Fclk: 125MHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 3 V ~ 5.5 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Supplier Package: LQFP
• Resolution: 14 Bit
• Maximum Input Frequency: 125(Min) MHz
• Tuning Word Width: 48 Bit
• Minimum Operating Supply Voltage: 4.5 V
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Supply Voltage: 5.5 V
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 85 °C
• Mounting: Surface Mount
• Ic Function: Direct Digital Synthesizer
• Supply Voltage Range: 4.5V To 5.5V, 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Control Register Description
NOTE:
14. b = binary, h = hex
ADDRESS
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
BITS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:5
7:0
4:0
7:0
5:4
7:0
4
3
2
1
0
7
6
5
Serial input control word.
Center frequency bits CF(7:0) (LSB).
Center frequency bits CF(15:8).
Center frequency bits CF(23:16).
Center frequency bits CF(31:24).
Center frequency bits CF(39:32).
Center frequency bits CF(47:40) (MSB). (Reset gives
Offset frequency bits OF(7:0) (LSB).
Offset frequency bits OF(15:8).
Offset frequency bits OF(23:16).
Offset frequency bits OF(31:24).
Offset frequency bits OF(39:32).
Offset frequency bits OF(47:40) (MSB).
Select number of serial frequency input bits:
1xx = 40-bit word (weighting same as CF(47:8))
011 = 32-bit word (weighting same as CF(47:16))
010 = 24-bit word (weighting same as CF(47:24))
001 = 16-bit word (weighting same as CF(47:32))
000 = 8-bit word (weighting same as CF(47:40))
Serial input sync position select:
1 = sync early. Sync is expected one serial clock period before the first data bit.
0 = sync late. Sync is expected one serial clock after the last data bit.
Serial sync polarity: 1 = active low, 0 = active high.
Serial clock polarity: 0 = rising edge, 1 = falling edge.
Shift direction: 0 = MSB first, 1 = LSB first.
Center frequency enable: 1 = enable, 0 = disable.
This bit can be used to zero the center frequency (CF(47:0)) to the phase accumulator. This does not zero
the processor interface registers—just the data path from the center frequency register to the phase
accumulator. The center frequency resets to f
NCO control word.
Intersil reserved. Do not change.
Serial output frequency register enable: 1 = enable, 0 = disable.
This bit enables/disables the data path from the serial frequency register to the phase accumulator,
without changing the value of the register. Should be disabled after RESET if not used.
Phase accumulator feedback: 0 = accumulator feedback disabled, 1 = accumulator enabled.
Intersil reserved. Do not change.
Test and timing control register. User must write 00h or 30h to register 14 after RESET.
NCO-to-DAC setup and hold timing control. Write either 11b or 00b to these bits.
Register 15 does not actually exist. Any write to register 15 is an UPDATE. This function is provided to
save one microprocessor control pin from being used for the UPDATE pin, if the user chooses.
16
ISL5314
DESCRIPTION
CLK
/4.
f
CLK /4 output).
January 19, 2010
(Note 14)
RESET
11000b
STATE
000b
00h
00h
00h
00h
00h
40h
00h
00h
00h
00h
00h
00h
01h
F8h
10h
01b
N/A
0b
0b
0b
0b
1b
1b
1b
1b
FN4901.3