CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 77

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
Media Interface Pins
RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7.
SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8.
TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4.
General Pins
CLK25 - 25 MHz Clock. Output, Pin 17.
RES - Reference Resistor. Input, Pin 86.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output
waveform. The rise and fall times are symmetric.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer primary.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer primary.
PECL output pair receives 100 Mb/s NRZI-encoded data from an external optical module.
PECL input pair receives signal detection indication from an external optical module.
PECL output pair drives 100 Mb/s NRZI-encoded data to an external optical module.
A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference
transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode
Initialization pin (TCM) for more information on TX_CLK operating modes.
CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer
Configuration Register (address 17h).
This input should be connected to ground with a 4.99 kΩ +/-1% series resistor. The resistor is needed
for the biasing of internal analog circuits.
TXSLEW0 pin
floating
floating
floating
high
high
high
low
low
low
TXSLEW1 mode
floating
floating
floating
high
high
high
low
low
low
Rise/Fall time
0.5 ns
1.0 ns
1.5 ns
2.0 ns
2.5 ns
3.0 ns
3.5 ns
4.0 ns
4.5 ns
CS8952
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