PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 13

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.1
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 2-2.
FIGURE 2-2:
EXAMPLE 2-1:
 2003 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction
Cycle
SUB_1
PORTA, 3
CLKOUT
OSC1
PC
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Fetch 1
Q2
PC
Q3
Execute 1
Fetch 2
Q4
Preliminary
Q1
Execute INST (PC)
Execute 2
Fetch INST (PC+1)
Fetch 3
Q2
PC+1
2.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change, (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 2-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Fetch 4
Instruction Flow/Pipelining
Q4
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
PIC16F62X
PC+2
Q3
DS40300C-page 11
Q4
Internal
phase
clock