DS90CF364AMTD/NOPB National Semiconductor, DS90CF364AMTD/NOPB Datasheet - Page 13

• Manufacturer Part Number: DS90CF364AMTD/NOPB
• Description: IC RCVR LVDS FPD 18BIT 48-TSSOP
• Manufacturer: National Semiconductor
• Type: Driverr

Specifications of DS90CF364AMTD/NOPB

• Number Of Drivers/receivers: 1/0
• Protocol: RS644
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Number Of Drivers: 21
• Number Of Receivers: 3
• Data Rate: 1300 Mbps
• Operating Supply Voltage: 3.3 V
• Maximum Power Dissipation: 1890 mW
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 60mA
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: TSSOP
• No. Of Pins: 48
• Operating Temperature Range: -10°C To +70°C
• Msl: MSL 2 - 1 Year
• Bandwidth: 170GHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90CF364AMTD; *DS90CF364AMTD/NOPB; DS90CF364AMTD

TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
RTxCLK OUT+
TxCLK OUT−
PWR DWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
Note 11: ISI is dependent on interconnect length; may be zero.
DS90C363 Pin Description — FPD Link Transmitter
CC
Pin Name
CC
CC
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
No.
21
3
3
1
1
1
1
1
3
4
1
2
1
3
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
(Continued)
FIGURE 19. Receiver LVDS Input Skew Margin
13
Description
DS012886-11
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