DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet
DP83849CVS/NOPB
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DP83849CVS/NOPB Summary of contents
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... Ethernet implementation for the system designer. System Diagram MII/RMII/SNI MPU/CPU MII/RMII/SNI PHYTER is a registered trademark of National Semiconductor Corporation © 2008 National Semiconductor Corporation Features • Low-power 3.3V, 0.18 m CMOS technology • Low power consumption <600mW Typical • ...
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PORT A MII/RMII/SNI TX RX 10/100 PHY CORE PORT A LED DRIVERS LEDS TPTD± TPRD± www.national.com MII MANAGEMENT INTERFACE MDC MDIO MANAGEMENT INTERFACE BOUNDARY SCAN JTAG Figure 1. DP83849I Functional Block Diagram 2 PORT B MII/RMII/SNI TX RX 10/100 PHY ...
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Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page 7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page ...
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Single Clock MII (SCMII) Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1. DP83849I Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Layout CRS_B/CRS_DV_B/LED_CFG_B 61 RX_DV_B/MII_MODE_B 62 RX_CLK_B 63 IOGND3 64 IOVDD3 65 66 MDIO 67 MDC CLK2MAC RESET_N 71 TCK 72 TDO 73 TMS 74 75 TRSTN TDI 76 IOGND4 77 IOVDD4 78 RX_CLK_A 79 ...
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Pin Descriptions The DP83849I pins are classified into the following inter- face categories (each interface is described in the sections that follow): — Serial Management Interface — MAC Data Interface — Clock Interface — LED Interface — JTAG Interface ...
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Signal Name Type RX_CLK_A O RX_CLK_B RX_DV_A O RX_DV_B RX_ER_A O RX_ER_B RXD[3:0]_A O RXD[3:0]_B CRS_A/CRS_DV_A O CRS_B/CRS_DV_B COL_A O COL_B Pin # 79 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 ...
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Clock Interface Signal Name Type X1 X2 CLK2MAC 1.4 LED Interface The DP83849I supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode strap and a third operational mode which Signal ...
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JTAG Interface Signal Name Type TCK I, PU TDO O TMS I, PU TRSTN I, PU TDI I, PU 1.6 Reset and Power Down Signal Name Type RESET_N I, PU PWRDOWN_INT_A I, PU PWRDOWN_INT_B 1.7 Strap Options The DP83849I ...
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Signal Name Type AN_EN (LED_ACT/LED_COL_A) AN1_A (LED_SPEED_A) AN0_A (LED_LINK_A) AN_EN (LED_ACT/LED_COL_B) AN1_B (LED_SPEED_B) AN0_B (LED_LINK_B) MII_MODE_A (RX_DV_A SNI_MODE_A (TXD3_A) MII_MODE_B (RX_DV_B) SNI_MODE_B (TXD3_B) LED_CFG_A (CRS_A/CRS_DV_A) LED_CFG_B (CRS_B/CRS_DV_B) www.national.com Pin # Description ...
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Signal Name Type MDIX_EN_A (RX_ER_A MDIX_EN_B (RX_ER_B) ED_EN_A (RXD3_A ED_EN_B (RXD3_B) CLK2MAC_DIS (RXD2_A EXTENDER_EN (RXD2_B Pin # Description 2 MDIX ENABLE: Default is to enable MDIX. This strapping ...
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Mb/s and 100 Mb/s PMD Interface Signal Name Type TPTDM_A I/O TPTDP_A TPTDM_B TPTDP_B TPRDM_A I/O TPRDP_A TPRDM_B TPRDP_B 1.9 Special Connections Signal Name Type RBIAS PFBOUT PFBIN1 PFBIN2 PFBIN3 PFBIN4 1.10 Power Supply Pins Signal Name IOVDD1, ...
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Package Pin Assignments VHB80A Pin Pin Name # 1 CRS_A/CRS_DV_A/LED_CFG_A 2 RX_ER_A/MDIX_EN_A 3 COL_A 4 RXD0_A/PHYAD1 5 RXD1_A/PHYAD2 6 COREGND1 7 PFBIN1 8 RXD2_A/CLK2MAC_DIS 9 RXD3_A/ED_EN_A 10 IOGND1 11 IOVDD1 12 TX_CLK_A 13 TX_EN_A 14 TXD0_A 15 TXD1_A 16 ...
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Configuration This section includes information on the various configura- tion options available with the DP83849I. The configuration options described below include: — Media Configuration — Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate ...
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Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the technology that is used. The Auto-Negotiation Link Partner (ANLPAR) at address 05h is used to receive the base link code word as ...
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MDIO bus in a system must have a unique physical address. The DP83849I supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30 (<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). ...
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LED Interface The DP83849I supports three configurable Light Emitting Diode (LED) pins for each port. Several functions can be multiplexed onto the three LEDs using three different modes of operation. The LED opera- tion mode can be selected by ...
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AN1_A = 1 AN_EN_A = 0 GND Figure 3. AN Strapping and LED Loading Example 2.4.2 LED Direct Control The DP83849I provides another option to directly control any or all LED outputs through the LED Direct Control Reg- ister (LEDCR), ...
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MAC Interface The DP83849I supports several modes of operation using the MII interface pins. The options are defined in the follow- ing sections and include: — MII Mode — RMII Mode — Serial Network Interface (SNI) — ...
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Reduced MII Interface The DP83849I incorporates the Reduced Media Indepen- dent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s ...
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Mb Serial Network Interface (SNI) The DP83849I incorporates Serial Network Inter- face (SNI) which allows a simple serial data interface for 10 Mb only devices. This is also referred 7-wire inter- face. ...
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Flexible MII Port Assignment The DP83849I supports a flexible assignment scheme for each of the channels to the MII/RMII interface. Either of the MII ports may be assigned to the internal channels A/B. These values are controlled by the ...
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RX MII Port Mapping Note that Channel A is the master of MII Port A, and Chan- nel B is the master of MII Port B. This means that in order for Channel B to control MII Port A, ...
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TX MII Port Mapping TX MII Port Mapping controls and configurations are shown in the following tables: RBR[10: Channel A RBR[10: 3.5.3 Common Flexible MII Port Configurations Table 10. Common Flexible ...
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Strapped Extender Mode The DP83849I provides a simple strap option to automati- cally configure both channels for Extender Mode with no device register configuration EXTENDER_EN Strap can be used in conjunction with the Auto-Negotiation Straps (AN_EN, AN0, AN1), the ...
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MII Serial Management Interface 3.6.1 Serial Management Register Access The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are acces- sible through the management interface pins MDC and MDIO. The DP83849I ...
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MDC Z MDIO (STA Opcode PHY Address Idle Start (Write) (PHYAD = 0Ch) Figure 6. Typical MDC/MDIO Write Operation 3.6.3 Serial Management Preamble Suppression The ...
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Architecture This section describes the operations within each trans- ceiver module, 100BASE-TX and 10BASE-T. Each opera- tion consists of several functional blocks and described in the following: — 100BASE-TX Transmitter — 100BASE-TX Receiver — 10BASE-T Transceiver Module 4.1 100BASE-TX ...
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Table 13. 4B5B Code-Group Encoding/Decoding DATA CODES IDLE AND CONTROL CODES INVALID CODES ...
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Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to ...
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RX_DV/CRS RX_CLK RX_DATA VALID SSD DETECT Figure 8. 100BASE-TX Receive Block Diagram RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD 35 ...
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Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the fre- quency content of the transmitted signal can vary greatly ...
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Base Line Wander Compensation The DP83849I is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP- PMD defined “killer” pattern. BLW can generally be defined as the change ...
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Descrambler A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the origi- nal unscrambled data (UD) from the scrambled data (SD) as ...
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Once this first squelch level is overcome cor- rectly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input ...
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Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simulta- neously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a ...
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Design Guidelines 5.1 TPI Network Circuit Figure 12 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. TPRDM 49.9 49.9 TDRDP TPTDM 49.9 49.9 TPTDP PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE. Figure 12. 10/100 Mb/s ...
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ESD Protection Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences ...
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Parameter Min Frequency Frequency Tolerance Frequency Stability Rise / Fall Time Jitter Jitter Symmetry 40% 1 This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock ...
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Power Down/Interrupt The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default, this pin func- tions as a power down input and the interrupt function is disabled. Setting bit 0 ...
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Cable Length Estimation The DP83849I provides a method of estimating cable length based on electrical characteristics of the 100Mb Link. This essentially provides an effective cable length rather than a measurement of the physical cable length. The cable ...
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Table 17. Link Quality Monitor Parameter Ranges Parameter Minimum Value DEQ C1 -128 DAGC DBLW -128 Freq Offset -128 Freq Control -128 5.7.3 TDR Cable Diagnostics The DP83849I implements a Time Domain Reflectometry (TDR) method of cable length measurement and ...
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Receive Window: The receiver can monitor receive data within a programmable window using the TDR Win- dow Register (TDR_WIN), address 17h. The window is controlled by two register values: TDR Start Window, bits [15:8] of TDR_WIN (17h) and TDR ...
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Reset Operation The DP83849I includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal opera- tion, the device can be reset by a hardware ...
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Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-Fh 8-15 10h 16 RO 11h ...
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Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
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Basic Mode Control Register (BMCR) Table 20. Basic Mode Control Register (BMCR), address 00h Bit Bit Name Default 15 RESET 0, RW/SC 14 LOOPBACK 13 SPEED Strap, RW SELECTION 12 AUTO-NEGOTI- Strap, RW ATION ENABLE 11 POWER DOWN 10 ...
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Table 20. Basic Mode Control Register (BMCR), address 00h (Continued) Bit Bit Name Default 7 COLLISION 0, RW TEST 6:0 RESERVED 0, RO Description Collision Test Collision test enabled Normal operation. When set, this bit will ...
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Basic Mode Status Register (BMSR) Table 21. Basic Mode Status Register (BMSR), address 01h Bit Bit Name 15 100BASE-T4 14 100BASE-TX FULL DUPLEX 13 100BASE-TX HALF DUPLEX 12 10BASE-T FULL DUPLEX 11 10BASE-T HALF DUPLEX 10:7 RESERVED 6 MF ...
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The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83849I. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may ...
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Table 24. Negotiation Advertisement Register (ANAR), address 04h (Continued) Bit Bit Name 11 ASM_DIR 10 PAUSE TX_FD 10_FD 5 10 4:0 SELECTOR www.national.com Default 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 25. Auto-Negotiation Link Partner Ability ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h Bit Bit Name ACK ACK2 11 TOGGLE 10:0 CODE www.national.com Default 0, RO ...
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Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 27. Auto-Negotiate Expansion Register (ANER), address 06h Bit Bit Name 15:5 RESERVED 4 PDF 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX 0 LP_AN_ABLE Default ...
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Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h Bit Bit Name ...
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PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name 15 RESERVED 14 MDIX MODE 13 RECEIVE ...
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Table 29. PHY Status Register (PHYSTS), address 10h Bit Bit Name 6 REMOTE FAULT 5 JABBER DETECT 4 AUTO-NEG COM- PLETE 3 LOOPBACK STA- TUS 2 DUPLEX STATUS 1 SPEED STATUS 0 LINK STATUS www.national.com Default 0, RO Remote Fault: ...
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MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the ...
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Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h 11 DUP_INT 10 ANC_INT 9 FHF_INT 8 RHF_INT 7 LQ_INT_EN 6 ED_INT_EN 5 LINK_INT_EN 4 SPD_INT_EN 3 DUP_INT_EN 2 ANC_INT_EN 1 FHF_INT_EN 0 RHF_INT_EN 7.1.13 Page Select Register ...
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Extended Registers - Page 0 7.2.1 False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 33. ...
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Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h (Continued) Bit Bit Name 8 SD_OPTION 7 DESC_TIME 6 RESERVED 5 FORCE_100_OK 4:3 RESERVED 2 NRZI_BYPASS 1:0 RESERVED www.national.com Default 1, RW Signal Detect Option Default ...
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RMII and Bypass Register (RBR) This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath ...
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Table 36. RMII and Bypass Register (RBR), addresses 17h (Continued) Bit Bit Name 5 RMII_MODE 4 RMII_REV1_0 3 RX_OVF_STS 2 RX_UNF_STS 1:0 ELAST_BUF[1:0] www.national.com Default Strap, RW Reduced MII Mode Standard MII Mode 1 = Reduced MII Mode ...
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LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency. ...
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PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also pro- vides Pause Negotiation status. Table 38. PHY Control Register (PHYCR), address 19h Bit Bit Name 15 ...
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Table 38. PHY Control Register (PHYCR), address 19h (Continued) Bit Bit Name 6 LED_CNFG[1] 5 LED_CNFG[0] 4:0 PHYADDR[4:0] 7.2.7 10 Base-T Status/Control Register (10BTSCR) This register is used for control and status for 10BASE-T device operation. Table 39. 10Base-T Status/Control ...
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Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah (Continued) Bit Bit Name 8 LOOPBACK_10_DIS 7 LP_DIS 6 FORCE_LINK_10 5 RESERVED 4 POLARITY 3 RESERVED 2 RESERVED 1 HEARTBEAT_DIS 0 JABBER_DIS www.national.com Default 0, RW 10Base-T Loopback Disable: In half-duplex mode, ...
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CD Test and BIST Extensions Register (CDCTRL1) This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. Table 40. CD Test and BIST Extensions Register (CDCTRL1), ...
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Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 42. Energy Detect Control (EDCR), address 1Dh Bit Bit Name 15 ED_EN 14 ED_AUTO_UP 13 ED_AUTO_DOWN 12 ED_MAN 11 ED_BURST_DIS 10 ED_PWR_STATE 9 ...
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Link Diagnostics Registers - Page 2 Page 2 Link Diagnostics Registers are accessible by setting bits [1: PAGESEL (13h). 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h 7.3.1 This register contains linked cable length estimation ...
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TDR Control Register (TDR_CTRL) 7.3.3 This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain ...
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TDR Window Register (TDR_WIN), Page 2, address 17h This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two val- ues contained in this register specify the beginning and end times for the window ...
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Variance Control Register (VAR_CTRL), Page 2, address 1Ah The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise ...
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Link Quality Monitor Register (LQMR), Page 2, address 1Dh This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds ...
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Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also pro- vides a mechanism for reading current adapted parameter values. Threshold values may not be ...
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Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Lead ...
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Symbol Pin Types Parameter SD PMD Input 100BASE-TX THon Pair Signal detect turn- on threshold SD PMD Input 100BASE-TX THoff Pair Signal detect turn- off threshold V PMD Input 10BASE-T Re- TH1 Pair ceive Threshold I Supply 100BASE-TX dd100 (Full ...
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AC Specs 8.2.1 Power Up Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses ...
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Reset Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for reg- ister accesses T2.2.2 Hardware Configuration Latch- ...
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MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 8.2.4 100 Mb/s ...
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Mb/s MII Receive Timing RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode Note: RX_CLK may be held low or high for a longer period ...
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MII Transmit Packet Deassertion Timing TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the ...
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Transmit Timing (t PMD Output Pair T2.8.2 PMD Output Pair eye pattern Parameter Description T2.8.1 100 Mb/s PMD Output Pair t and t F 100 Mb/s t and T2.8.2 100 Mb/s PMD Output Pair Transmit ...
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MII Receive Packet Latency Timing PMD Input Pair IDLE T2.9.1 CRS RXD[3:0] RX_DV RX_ER Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the ...
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Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise Note: An attached Mac should drive the transmit signals ...
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Mb/s Serial Mode Transmit Timing T2.13.1 TX_CLK TXD[0] TX_EN Parameter Description T2.13.1 TX_CLK High Time T2.13.2 TX_CLK Low Time T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 8.2.14 10 Mb/s ...
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Transmit Timing (Start of Packet) TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.15.1 Transmit Output Delay from the Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = ...
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Receive Timing (Start of Packet TPRD T2.17.1 CRS RX_CLK T2.17.2 RX_DV 0000 RXD[3:0] Parameter Description T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency T2.17.3 Receive Data Latency Note: 10BASE-T ...
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Mb/s Heartbeat Timing TX_EN TX_CLK COL Parameter Description T2.19.1 CD Heartbeat Delay T2.19.2 CD Heartbeat Duration 8.2.20 10 Mb/s Jabber Timing TXE PMD Output Pair COL Parameter Description T2.20.1 Jabber Activation Time T2.20.2 Jabber Deactivation Time www.national.com T2.19.2 ...
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Normal Link Pulse Timing Normal Link Pulse(s) Parameter Description T2.21.1 Pulse Width T2.21.2 Pulse Period Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.1 Fast Link Pulse(s) Parameter Description T2.22.1 Clock, Data Pulse ...
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Signal Detect Timing PMD Input Pair T2.23.1 SD+ internal Parameter Description T2.23.1 SD Internal Turn-on Time T2.23.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback ...
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Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T2.25.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. T2.25.1 Notes 10 Mb/s internal ...
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RMII Transmit Timing X1 TXD[1:0] TX_EN PMD Output Pair Parameter Description T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising T2.26.4 X1 Clock to PMD Output Pair Latency ...
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RMII Receive Timing IDLE (J/K) PMD Input Pair X1 T2.27.3 RX_DV CRS_DV RXD[1:0] RX_ER Parameter Description T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb) T2.27.4 CRS OFF ...
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Single Clock MII (SCMII) Transmit Timing X1 TXD[3:0] TX_EN PMD Output Pair Parameter Description T2.28.1 X1 Clock Period T2.28.2 TXD[3:0], TX_EN Data Setup T2.28.3 TXD[3:0], TX_EN Data Hold T2.28.4 X1 Clock to PMD Output Pair Latency (100Mb) Note: Latency ...
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Single Clock MII (SCMII) Receive Timing IDLE (J/K) PMD Input Pair X1 T2.29.3 CRS RX_DV RXD[1:0] RX_ER Parameter Description T2.29.1 X1 Clock Period T2.29.2 RXD[3:0], RX_DV and RX_ER output delay T2.29.3 CRS ON delay (100Mb) T2.29.4 CRS OFF delay ...
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Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) MODE Parameter Description T2.30.1 From software clear of bit 10 in the BMCR register to the transi- tion from Isolate to Normal Mode 8.2.31 CLK2MAC ...
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Mb TX_CLK Timing X1 TX_CLK Parameter Description T2.32 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. T2.32.1 ...
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