CLC006BM/NOPB National Semiconductor, CLC006BM/NOPB Datasheet - Page 9

IC CABLE DVR DGTL SER ADJ 8-SOIC

CLC006BM/NOPB

Manufacturer Part Number
CLC006BM/NOPB
Description
IC CABLE DVR DGTL SER ADJ 8-SOIC
Manufacturer
National Semiconductor
Series
CLCr
Type
Driverr
Datasheet

Specifications of CLC006BM/NOPB

Number Of Drivers/receivers
1/0
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
For Use With
SD901EVK - BOARD EVAL CLC014, 016, 011, 006SD006EVK - BOARD EVALUATION CLC006
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Protocol
-
Other names
CLC006BM
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or other-
wise, may be reduced by placing the output back-match
resistor close to the output pin and by minimizing all intercon-
necting trace lengths. Figure 13 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
9
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC006. The following guidelines will aid in achieving satis-
factory device performance.
Use a ground plane or power/ground plane sandwich
design for optimum performance.
Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1” (2.5 mm) from the
device power pins.
Provide short, symmetrical ground return paths for:
— inputs,
— supply bypass capacitors and
— the output load.
Provide short, grounded guard traces located
— under the centerline of the package,
— 0.1” (2.5 mm) from the package pins
— on both top and bottom of the board with connecting
vias.
FIGURE 13. Rise Time vs C
L
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