PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 143

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.2
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
15.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
15.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
FIGURE 15-1:
 2004 Microchip Technology Inc.
Note:
Capture Mode
CCP PIN CONFIGURATION
If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
TIMER1/TIMER3 MODE SELECTION
CCP1 pin
CCP2 pin
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0>
CCP2CON<3:0>
Prescaler
Prescaler
1, 4, 16
1, 4, 16
Q1:Q4
4
Edge Detect
Edge Detect
4
4
and
and
PIC18F2420/2520/4420/4520
Preliminary
Set CCP2IF
Set CCP1IF
T3CCP1
T3CCP2
T3CCP2
T3CCP1
T3CCP2
T3CCP2
15.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM3:CCPxM0). Whenever
the CCP module is turned off or Capture mode is
disabled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1:
CLRF
MOVLW
MOVWF
CCP2CON
NEW_CAPT_PS ; Load WREG with the
CCP2CON
SOFTWARE INTERRUPT
CCP PRESCALER
TMR3
Enable
TMR1
Enable
TMR3
Enable
TMR1
Enable
CCPR1H
CCPR2H
TMR3H
TMR3H
TMR1H
TMR1H
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
; Turn CCP module off
; new prescaler mode
; value and CCP ON
; Load CCP2CON with
; this value
CCPR1L
CCPR2L
TMR1L
TMR1L
TMR3L
TMR3L
DS39631A-page 141