PIC16F84A-20/P Microchip Technology Inc., PIC16F84A-20/P Datasheet - Page 32
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PIC16F84A-20/P
Manufacturer Part Number
PIC16F84A-20/P
Description
18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F84A-20P.pdf
(88 pages)
Specifications of PIC16F84A-20/P
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
13
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
68 Bytes
Speed
20 MHz
Timers
1-8-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer:
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PIC16F84A
6.9
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
The code in Example 6-1 stores and restores the
STATUS and W register’s values. The user defined
registers, W_TEMP and STATUS_TEMP are the tem-
porary storage locations for the W and STATUS
registers values.
EXAMPLE 6-1:
6.10
The Watchdog Timer is a free running On-Chip RC
Oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 6.1).
DS35007B-page 30
PUSH
ISR
POP
Context Saving During Interrupts
Watchdog Timer (WDT)
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
MOVWF
SWAPF
SWAPF
W_TEMP
STATUS,
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,
W_TEMP,
SAVING STATUS AND W REGISTERS IN RAM
W
F
W
; Copy W to TEMP register,
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
; Interrupt Service Routine
; should configure Bank as required
;
; Swap nibbles in STATUS_TEMP register
; and place result into W
; Move W into STATUS register
; (sets bank to original state)
; Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
Example 6-1 does the following:
a)
b)
c)
d)
e)
6.10.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, V
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
Stores the W register.
Stores the STATUS register in STATUS_TEMP.
Executes the Interrupt Service Routine code.
Restores the STATUS (and bank select bit)
register.
Restores the W register.
WDT PERIOD
DD
and process variations from part to
2001 Microchip Technology Inc.