LAN8710AI-EZK SMSC, LAN8710AI-EZK Datasheet - Page 11

• Manufacturer Part Number: LAN8710AI-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710AI-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Product: Ethernet Transceivers
• Standard Supported: 802.3, 802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• For Use With: 638-1098 - EVALUATION BOARD FOR LAN8710
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1083; LAN8710AI-EZK

Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Datasheet
SMSC LAN8710A/LAN8710Ai
NUM PINS
1
1
1
1
PHY Address
Configuration
Configuration
Configuration
Configuration
Mode Select
(MII Mode)
(MII Mode)
Operating
Operating
MII/RMII
Receive
Receive
Receive
Receive
Mode 0
Mode 1
NAME
Data 0
Data 1
Data 2
Data 3
Strap
Strap
Strap
Strap
PHY
PHY
2
SYMBOL
RMIISEL
PHYAD2
MODE0
MODE1
Table 2.1 MII/RMII Signals (continued)
RXD0
RXD1
RXD2
RXD3
DATASHEET
BUFFER
TYPE
VO8
(PU)
VO8
(PU)
VO8
(PD)
VO8
(PD)
VIS
VIS
VIS
VIS
11
®
Technology
Bit 0 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
Combined with MODE1 and MODE2, this
configuration strap sets the default PHY mode.
See
configuration straps.
Note:
Bit 1 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
Combined with MODE0 and MODE2, this
configuration strap sets the default PHY mode.
See
configuration straps.
Note:
Bit 2 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note:
This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS,
MII Mode is selected. When strapped high to
VDDIO RMII Mode is selected.
See
configuration straps.
Note:
Bit 3 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note:
Combined with PHYAD0 and PHYAD1, this
configuration strap sets the transceiver’s SMI
address.
See
configuration straps.
Note:
Note 2.1
Note 2.1
Note 2.1
Note 2.1
Refer to
Mode Configuration," on page 35
additional details.
Refer to
Mode Configuration," on page 35
additional details.
This signal is not used in RMII Mode.
Refer to
MII/RMII Mode Configuration," on
page 36
This signal is not used in RMII Mode.
Refer to
PHY Address Configuration," on
page 35
for more information on
for more information on
for more information on
for more information on
DESCRIPTION
Section 3.7.2, "MODE[2:0]:
Section 3.7.2, "MODE[2:0]:
Section 3.7.3, "RMIISEL:
for additional details.
Section 3.7.1, "PHYAD[2:0]:
for additional information.
Revision 1.2 (11-10-10)
for
for