LAN8710AI-EZK SMSC, LAN8710AI-EZK Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/6/617/smsc_sml.jpg)
LAN8710AI-EZK
Manufacturer Part Number
LAN8710AI-EZK
Description
TXRX ETHERNET 10/100 MII/RMII
Manufacturer
SMSC
Type
Transceiverr
Datasheets
1.LAN8720AI-CP.pdf
(2 pages)
2.LAN8710AI-EZK.pdf
(4 pages)
3.LAN8710A-EZK-TR.pdf
(81 pages)
Specifications of LAN8710AI-EZK
Number Of Drivers/receivers
4/4
Protocol
MII, RMII
Voltage - Supply
1.6 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
32-QFN
Product
Ethernet Transceivers
Standard Supported
802.3, 802.3u
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.6 V
Maximum Operating Temperature
+ 85 C
Ethernet Connection Type
10/100 Base-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
For Use With
638-1098 - EVALUATION BOARD FOR LAN8710
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1083
LAN8710AI-EZK
LAN8710AI-EZK
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN8710AI-EZK
Manufacturer:
Standard
Quantity:
4 529
Company:
Part Number:
LAN8710AI-EZK
Manufacturer:
GASIN
Quantity:
6 271
Part Number:
LAN8710AI-EZK
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
LAN8710AI-EZK-TR
Manufacturer:
SMSC20
Quantity:
403
Revision 1.2 (11-10-10)
5.5.3
Configuration Strap
Configuration Strap
Pins Output Drive
SYMBOL
t
t
Power Supplies
t
purstd
purstv
t
t
t
t
odad
otaa
rstia
css
csh
All External
Pins Input
Power-On nRST & Configuration Strap Timing
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to
power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation,
nRST must be asserted for no less than t
not be deasserted before t
operating levels. In order for valid configuration strap values to be read at power-up, the t
timing constraints must be followed. Refer to
information.
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to
Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.
External power supplies at 80% to nRST deassertion
External power supplies at 80% to nRST valid
nRST input assertion time
Configuration strap pins setup to nRST deassertion
Configuration strap pins hold after nRST deassertion
Output tri-state after nRST assertion
Output drive after nRST deassertion
nRST
"Configuration Straps," on page 35
low and must not be driven as inputs.
Table 5.7 Power-On nRST & Configuration Strap Timing Values
Figure 5.3 Power-On nRST & Configuration Strap Timing
80%
DESCRIPTION
purstd
t
purstv
after all external power supplies have reached 80% of their nominal
DATASHEET
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
70
rstia
for details. Configuration straps must only be pulled high or
t
purstd
. The nRST pin can be asserted at any time, but must
Section 3.8.5, "Resets," on page 40
t
otaa
t
rstia
MIN
100
200
25
0
1
2
t
css
TYP
t
t
odad
csh
SMSC LAN8710A/LAN8710Ai
(Note
MAX
800
50
5.14)
for additional
Section 3.7,
css
Datasheet
®
UNITS
and t
Technology
mS
μ S
nS
nS
nS
nS
nS
csh