LAN8700IC-AEZG SMSC, LAN8700IC-AEZG Datasheet - Page 15

• Manufacturer Part Number: LAN8700IC-AEZG
• Description: TXRX ETHERNET 10/100 IND 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700IC-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: QFN
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Control Interface: MII, RMII
• Data Rate Max: 100Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 638-1047-6

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
SIGNAL NAME
SIGNAL NAME
SPEED100/
FDUPLEX/
FDUPLEX/
ACTIVITY/
ACTIVITY/
PHYAD1
PHYAD2
PHYAD3
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
MODE2
MODE1
MODE0
RXD2/
RXD1/
RXD0/
MDIO
LINK/
LINK/
CRS/
MDC
Table 3.4 Boot Strap Configuration Inputs
Table 3.2 LED Signals (continued)
TYPE
TYPE
IOPU
IOPU
IOPU
IOPD
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IPD
Table 3.3 Management Signals
DATASHEET
LED2 – LINK ON indication. Active indicates that the Link
(100Base-TX or 10Base-T) is on.
Note:
LED3 – ACTIVITY indication. Active indicates that there is
Carrier sense (CRS) from the active PMD.
Note:
LED4 – DUPLEX indication. Active indicates that the PHY is in
full-duplex mode.
Note:
Management Data Input/OUTPUT: Serial management data
input/output.
Management Clock: Serial management clock.
PHY Address Bit 4: set the default address of the PHY. This
signal is mux’d with CRS
Note:
PHY Address Bit 3: set the default address of the PHY.
Note:
PHY Address Bit 2: set the default address of the PHY.
Note:
PHY Address Bit 1: set the default address of the PHY.
Note:
PHY Address Bit 0: set the default address of the PHY.
Note:
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See
the MODE options.
Note:
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See
the MODE options.
Note:
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See
the MODE options.
Note:
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
®
15
Technology in a Small Footprint
This signal is mux’d with PHYAD1
This signal is mux’d with PHYAD2
This signal is mux’d with PHYAD3
This signal is mux’d with CRS
This signal is mux’d with FDUPLEX
This signal is mux’d with ACTIVITY
This signal is mux’d with LINK
This signal is mux’d with SPEED100
This signal is mux’d with RXD2
This signal is mux’d with RXD1
This signal is mux’d with RXD0
DESCRIPTION
DESCRIPTION
(Note
3.1)
Revision 2.2 (12-04-09)
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