PIC18F4520-I/PT Microchip Technology Inc., PIC18F4520-I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC18F4520-I/PT
• Description: 44 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
19.4
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power managed mode.
If the A/D is expected to operate while the device is in
a power managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in the Sleep mode requires the A/D F
clock to be selected. If bits ACQT2:ACQT0 are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39631A-page 230
Operation in Power Managed
Modes
Preliminary
RC
19.5
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (V
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
2: Analog levels on any pin defined as a dig-
3: The
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert as
analog inputs. Analog levels on a digitally
configured
converted.
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG0 bits in ADCON1 are
reset.
OH
or V
PBADEN
OL
 2004 Microchip Technology Inc.
) will be converted.
input
bit
will
in
be
Configuration
accurately