M25P64-VMF6P STMicroelectronics, M25P64-VMF6P Datasheet - Page 14

• Manufacturer Part Number: M25P64-VMF6P
• Description: 64 MBIT, LOW VOLTAGE, SERIAL FLASO 16 .30 LARGE JEDEC MS-013
• Manufacturer: STMicroelectronics

Specifications of M25P64-VMF6P

• Lead Free Status / Rohs Status: RoHS Compliant part

M25P64
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR), Read Identification
(RDID) or Read Electronic Signature (RES) in-
struction, the shifted-in instruction sequence is fol-
Table 4. Instruction Set
14/38
FAST_READ Read Data Bytes at Higher Speed
Instruction
WREN
WRSR
RDSR
READ
WRDI
RDID
RES
PP
SE
BE
Write Enable
Write Disable
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
Page Program
Sector Erase
Bulk Erase
Read Electronic Signature
Description
Table
4..
One-byte Instruction Code
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
0000 1011
1101 1000
1010 1011
1001 1111
1100 0111
lowed by a data-out sequence. Chip Select (S) can
be driven High after any bit of the data-out se-
quence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN) or Write Disable
(WRDI), Chip Select (S) must be driven High ex-
actly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Se-
lect (S) must driven High when the number of
clock pulses after Chip Select (S) being driven
Low is an exact multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
ABh
0Bh
D8h
C7h
06h
04h
9Fh
05h
01h
03h
02h
Address
Bytes
0
0
0
0
0
3
3
3
3
0
0
Dummy
Bytes
0
0
0
0
0
0
1
0
0
0
3
1 to 256
Bytes
1 to
1 to
1 to
1 to
1 to 3
Data
0
0
1
0
0