DS2148T+ Maxim Integrated Products, DS2148T+ Datasheet - Page 12

• Manufacturer Part Number: DS2148T+
• Description: IC LIU E1/T1/J1 5V 44-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS2148T+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,
DS2148T)
RCL/LOTC
BIS0/BIS1
ALE(AS)
D0/AD0
D7/AD7
RD(DS)
BPCLK
NAME
MCLK
RCLK
HRST
PBEO
PBTS
INT
NA
A0
A4
CS
to
to
32/33
PIN
11
31
19
12
29
23
30
24
44
40
25
to
to
7
4
1
2
-
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1),
serves as the address bus. In multiplexed bus operation (BIS1 = 0, BIS0 =
0), these pins are not used and should be tied low.
Address Latch Enable (Address Strobe). When using the parallel port
(BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to demultiplex the
bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),
should be tied low.
Bus Interface Select Bits 0 & 1. Used to select bus interface option. See
Table 2-1
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
clock output that is referenced to RCLK selectable via CCR5.7 and
CCR5.6. In hardware mode, defaults to 16.384MHz output.
Active-Low Chip Select. Must be low to read or write to the device.
Data Bus/Address/Data Bus. In non-multiplexed bus operation (BIS1 =
0, BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus.
Active-Low Hardware Reset. Bringing HRST low will reset the DS2148
setting all control bits to their default state of all zeros.
Active-Low Interrupt. Flags host controller during conditions and
change of conditions defined in the Status Register. Active low, open
drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is
applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is
optional.
See Note 1 on clock accuracy at the end of this table.
Not Assigned. Should be tied low.
PRBS Bit Error Output. The receiver will constantly search for a 2
a 2
out of synchronization with the PRBS pattern. Goes low when
synchronized to the PRBS pattern. Any errors in the received pattern after
synchronization will cause a positive going pulse (with same period as E1
or T1 clock) synchronous with RCLK. PRBS bit errors can also be
reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.
Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set
high to select Motorola bus timing, set low to select Intel bus timing. This
pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. If
PBTS = 1 and BIS1 = 0, then these pins assume the Motorola function
listed in parenthesis (). In serial port mode, this pin should be tied low.
Receive Clock. Buffered recovered clock from the line. Synchronous to
MCLK in absence of signal at RTIP and RRING.
Active-Low Read Input (Data Strobe). DS is active low when in
nonmultiplexed, Motorola mode. See the bus timing diagrams in Section
10.
Receive Carrier Loss/Loss of Transmit Clock. An output which will
toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high
if the TCLK pin has not been toggled for 5µs ±2µs (CCR2.7 = 1). CCR2.7
defaults to logic 0 when in hardware mode.
20
-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if
for details.
12 of 73
FUNCTION
15
-1 or