PIC16F873-20/SP Microchip Technology Inc., PIC16F873-20/SP Datasheet - Page 131
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PIC16F873-20/SP
Manufacturer Part Number
PIC16F873-20/SP
Description
28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F873-20SP.pdf
(218 pages)
Specifications of PIC16F873-20/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
22
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
192 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F873-20/SP
Manufacturer:
MIC
Quantity:
20 000
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12.10 Interrupts
The PIC16F87X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-9:
The following table shows which devices have which interrupts.
Note:
2001 Microchip Technology Inc.
PIC16F876/873
PIC16F877/874
CCP2IF
CCP2IE
Device
BCLIF
BCLIE
PSPIF
PSPIE
EEIF
EEIE
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
TMR1IF
TMR1IE
ADIF
ADIE
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
Yes
Yes
TMR2IF
TMR2IE
RCIF
RCIE
INTERRUPT LOGIC
Yes
Yes
CCP1IF
CCP1IE
SSPIF
SSPIE
TXIF
TXIE
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Yes
Yes
The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
Yes
Yes
Yes
Yes
Yes
Yes
PIC16F87X
Wake-up (If in SLEEP mode)
Yes
Yes
DS30292C-page 129
Interrupt to CPU
Yes
Yes
Yes
Yes
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