PIC16F873-20/SP Microchip Technology Inc., PIC16F873-20/SP Datasheet - Page 174
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PIC16F873-20/SP
Manufacturer Part Number
PIC16F873-20/SP
Description
28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F873-20SP.pdf
(218 pages)
Specifications of PIC16F873-20/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
22
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
192 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F873-20/SP
Manufacturer:
MIC
Quantity:
20 000
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PIC16F87X
TABLE 15-9:
DS30292C-page 172
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Param
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast mode (400 kHz) I
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Tsu:dat
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
released.
R
max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I
Thd:sta
Thd:dat
Tsu:sta
Tsu:dat
Tsu:sto
Thigh
Sym
Tlow
Tbuf
Taa
Cb
Tr
Tf
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
I
2
C BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
2
C bus device can be used in a standard mode (100 kHz) I
Characteristic
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1Cb
20 + 0.1Cb
0.5T
0.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
1000
3500
Max
300
300
300
0.9
400
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C bus specification) before the SCL line is
2
C bus system, but the requirement that
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2001 Microchip Technology Inc.
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for Repeated
START condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
Conditions
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