DSPIC30F6010A-30I/PT Microchip Technology Inc., DSPIC30F6010A-30I/PT Datasheet - Page 35

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DSPIC30F6010A-30I/PT

Manufacturer Part Number
DSPIC30F6010A-30I/PT
Description
16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC30F6010A-30I/PT

A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
4K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
144K Bytes
Ram Size
8K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part

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0
FIGURE 3-3:
3.1.2
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MS bit of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.5, DSP Engine.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically con-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and
higher, maps directly into a corresponding program
memory address (see Figure 3-4), only the lower
16-bits of the 24-bit program word are used to contain
the data. The upper 8 bits should be programmed to
force an illegal instruction to maintain machine robust-
ness. Refer to the Programmer’s Reference Manual
(DS70030) for details on instruction encoding.
 2004 Microchip Technology Inc.
PROGRAM SPACE VISIBILITY
FROM DATA SPACE
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
PC Address
0x000004
0x000006
0x000002
0x000000
PROGRAM DATA TABLE ACCESS (MS BYTE)
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 1)
Preliminary
23
Note that by incrementing the PC by 2 for each pro-
gram memory word, the LS 15 bits of data space
addresses directly map to the LS 15 bits in the corre-
sponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG<7:0>, as shown in Figure 3-4.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions will require one instruc-
• All other instructions will require two instruction
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances will require two instruction
• Any other iteration of the REPEAT loop will allow
16
Note:
tion cycle in addition to the specified execution
time:
- MAC class of instructions with data operand
- MOV instructions
- MOV.D instructions
cycles in addition to the specified execution time
of the instruction.
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
- Execution upon re-entering the loop after an
the instruction, accessing data using PSV, to
execute in a single cycle.
TBLRDH.W
pre-fetch
interrupt
interrupt is serviced
TBLRDH.B (Wn<0> = 0)
PSV access is temporarily disabled during
Table Reads/Writes.
8
dsPIC30F
DS70082G-page 33
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