PIC18F87K22-I/PTRSL Microchip Technology Inc., PIC18F87K22-I/PTRSL Datasheet - Page 26
PIC18F87K22-I/PTRSL
Manufacturer Part Number
PIC18F87K22-I/PTRSL
Description
128kB Flash, 4kB RAM, 1kB EE, nanoWatt XLP, GP, 80 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F67K22-IPTRSL.pdf
(548 pages)
Specifications of PIC18F87K22-I/PTRSL
A/d Inputs
24-Channel, 12-Bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
69
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.8K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
6-8-bit, 5-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K22 FAMILY
TABLE 1-4:
DS39960C-page 26
RB0/INT0/FLT0
RB1/INT1
RB2/INT2/CTED1
RB3/INT3/CTED2/
ECCP2/P2A
RB4/KBI0
RB5/KBI1/T3CKI/T1G
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend: TTL = TTL compatible input
Note 1:
RB0
INT0
FLT0
RB1
INT1
RB2
INT2
CTED1
RB3
INT3
CTED2
ECCP2
P2A
RB4
KBI0
RB5
KBI1
T3CKI
T1G
RB6
KBI2
PGC
RB7
KBI3
PGD
2:
3:
4:
5:
Pin Name
ST
I
P
I
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
Not available on PIC18F65K22 and PIC18F85K22 devices.
PSP is available only in Microcontroller mode.
The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
2
C = I
= Schmitt Trigger input with CMOS levels
= Input
= Power
2
PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
C™/SMBus
Pin Number
TQFP
58
57
56
55
54
53
52
47
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
Digital I/O.
External Interrupt 0.
Enhanced PWM Fault input for ECCP1/2/3.
Digital I/O.
External Interrupt 1.
Digital I/O.
External Interrupt 2.
CTMU Edge 1 input.
Digital I/O.
External Interrupt 3.
CTMU Edge 2 input.
Capture 2 input/Compare 2 output/PWM2 output.
Enhanced PWM 2 Output A.
Digital I/O.
Interrupt-on-change pin.
Digital I/O.
Interrupt-on-change pin.
Timer3 clock input.
Timer1 external clock gate input.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
= Output
= Open-Drain (no P diode to V
Description
2011 Microchip Technology Inc.
DD
)
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