PIC18F87K22-I/PTRSL Microchip Technology Inc., PIC18F87K22-I/PTRSL Datasheet - Page 320

• Manufacturer Part Number: PIC18F87K22-I/PTRSL
• Description: 128kB Flash, 4kB RAM, 1kB EE, nanoWatt XLP, GP, 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F87K22-I/PTRSL

• A/d Inputs: 24-Channel, 12-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 69
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.8K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 6-8-bit, 5-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Following this, the ACKEN bit is automatically cleared, the
PIC18F87K22 FAMILY
21.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Gen-
erator then counts for one rollover period (T
SCLx pin is deasserted (pulled high). When the SCLx pin
is sampled high (clock arbitration), the Baud Rate Gener-
ator counts for T
Baud Rate Generator is turned off and the MSSP module
then goes into an inactive state
21.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25:
FIGURE 21-26:
DS39960C-page 320
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
Note: T
Sequence
BRG
Note: T
Write to SSPxCON2,
SSPxIF
SDAx
SCLx
Falling Edge of
9th Clock
; the SCLx pin is then pulled low.
Acknowledge Sequence Starts Here,
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
ACK
= one Baud Rate Generator period.
= one Baud Rate Generator period.
Set PEN
SSPxIF Set at
the End of Receive
Enable
(Figure
ACKEN = 1, ACKDT = 0
Write to SSPxCON2,
21-25).
T
T
bit,
BRG
BRG
SDAx Asserted Low Before Rising Edge of Clock
to Set up Stop Condition
BRG
8
D0
) and the
ACKEN
T
SCLx Brought High After T
BRG
Cleared in
Software
P
T
BRG
SCLx = 1 for T
after SDAx Sampled High. P bit (SSPxSTAT<4>) is Set
T
BRG
ACK
21.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set
21.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
PEN bit (SSPxCON2<2>) is Cleared by
T
BRG
Hardware and the SSPxIF bit is Set
9
SSPxIF Set at the End
of Acknowledge Sequence
BRG
BRG
, Followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN Automatically Cleared
(Baud Rate Generator rollover count)
 2011 Microchip Technology Inc.
Cleared in
Software
BRG
BRG
(Figure
later, the PEN bit is
21-26).