PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 102

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PIC12C671-04I/P

Manufacturer Part Number
PIC12C671-04I/P
Description
8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12C671-04I/P

A/d Inputs
4-Channel, 8-Bit
Cpu Speed
2.5 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
PIC12C67X
FIGURE 12-6: CLKOUT AND I/O TIMING
TABLE 12-3:
DS30561B-page 102
Note 1:
Param
CLKOUT
22††*
23††*
18A*
20A*
21A*
No.
10*
11*
12*
13*
14*
15*
16*
17*
18*
19*
20*
21*
I/O Pin
(output)
I/O Pin
(input)
OSC1
*
††
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are asynchronous events not related to any internal clock edge.
Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x T
Sym
TosH2ckL OSC1 to CLKOUT
TosH2ckH OSC1 to CLKOUT
TckR
TckF
TckL2ioV
TioV2ckH Port in valid before CLKOUT
TckH2ioI
TosH2ioV OSC1 (Q1 cycle) to Port out valid
TosH2ioI
TioV2osH Port input valid to OSC1 (I/O in setup
TioR
TioF
Tinp
Trbp
Note: Refer to Figure 12-4 for load conditions.
CLKOUT AND I/O TIMING REQUIREMENTS
old value
Characteristic
CLKOUT rise time
CLKOUT fall time
CLKOUT
Port in hold after CLKOUT
OSC1 (Q2 cycle) to Port
input invalid (I/O in hold
time)
time)
Port output rise time
Port output fall time
GP2/INT pin high or low time
GP0/GP1/GP3 change INT high or low
time
Q4
to Port out valid
10
13
17
14
20, 21
Q1
PIC12C67X
PIC12LC67X
PIC12C67X
PIC12LC67X
PIC12C67X
PIC12LC67X
19
T
18
OSC
Min
100
200
T
T
0
0
CY
CY
+ 200
Q2
15
Typ†
75
75
35
35
50
10
10
0.5T
OSC
1999 Microchip Technology Inc.
Max
.
200
200
100
100
150
CY
11
40
80
40
80
12
+ 20
new value
16
Q3
Units Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1

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