PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 39
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PIC12C671-04I/P
Manufacturer Part Number
PIC12C671-04I/P
Description
8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12C671-04IP.pdf
(129 pages)
Specifications of PIC12C671-04I/P
A/d Inputs
4-Channel, 8-Bit
Cpu Speed
2.5 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
7.0
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the bit T0SE
FIGURE 7-1:
FIGURE 7-2:
1999 Microchip Technology Inc.
GP2/TOCKI/
AN2/INT
Instruction
TMR0
PC
(Program
Counter)
Fetch
Instruction
Executed
Note 1: TOCS, TOSE, PSA, PS<2:0> (OPTION<5:0>).
TIMER0 MODULE
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
TOSE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
F
OSC
PC-1
/4
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
T0+1
TOCS
PC
0
1
T0+2
Write TMR0
executed
Programmable
PC+1
PS<2:0>
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are dis-
cussed in detail in Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
7.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
NT0
Read TMR0
reads NT0
PC+3
(2 T
Timer0 Interrupt
Sync with
Internal
clocks
CY
delay)
Read TMR0
reads NT0
NT0
PC+4
PIC12C67X
Read TMR0
reads NT0 + 1
NT0+1
Data Bus
TMR0
PC+5
8
DS30561B-page 39
Read TMR0
reads NT0 + 2
Set interrupt
flag bit T0IF
on overflow
NT0+2
PC+6
T0