PIC16F1827-I/SS Microchip Technology Inc., PIC16F1827-I/SS Datasheet - Page 280
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F1827-I/SS
Manufacturer Part Number
PIC16F1827-I/SS
Description
20 SSOP .209in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC16F1827-I/SS
Manufacturer:
NELL
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45
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PIC16(L)F1826/27
REGISTER 25-2:
DS41391D-page 280
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
R/C/HS-0/0
WCOL
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I
SSPxADD value of ‘0’ is not supported. Use SSPxM = 0000 instead.
WCOL: Write Collision Detect bit
Master mode:
1 =
0 =
Slave mode:
1 =
0 =
SSPxOV: Receive Overflow Indicator bit
In SPI mode:
1 =
0 =
In I
1 =
0 =
SSPxEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 =
0 =
In I
1 =
0 =
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSPxM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = SPI Master mode, clock = F
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
R/C/HS-0/0
2
2
2
2
SSPxOV
C mode:
C mode:
C Slave mode:
C Master mode:
A write to the SSPxBUF register was attempted while the I
No collision
The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
No collision
A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
No overflow
A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode
(must be cleared in software).
No overflow
Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
SSPxCON1: SSPx CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SSPxEN
R/W-0/0
OSC
OSC
OSC
OSC
OSC
/(4 * (SSPxADD+1))
/4
/16
/64
/(4 * (SSPxADD+1))
(1)
R/W-0/0
CKP
2
C Mode.
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
R/W-0/0
(4)
(5)
2
C conditions were not valid for a transmission to be started
R/W-0/0
SSPxM<3:0>
2011 Microchip Technology Inc.
C = User cleared
R/W-0/0
(3)
(2)
R/W-0/0
bit 0
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