PIC16F628-20I/P Microchip Technology Inc., PIC16F628-20I/P Datasheet - Page 21
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PIC16F628-20I/P
Manufacturer Part Number
PIC16F628-20I/P
Description
18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F628-20IP.pdf
(170 pages)
Specifications of PIC16F628-20I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
16
Interface
SCI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
224 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F628-20I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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3.2.2.1
The STATUS register, shown in Register 3-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 3-1:
2003 Microchip Technology Inc.
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
STATUS Register
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
Legend:
R = Readable bit
-n = Value at POR
R/W-0
IRP
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
R/W-0
RP1
R/W-0
RP0
Preliminary
W = Writable bit
’1’ = Bit is set
R-1
TO
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: The C and DC bits operate as a Borrow
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-1
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
PD
R/W-x
PIC16F62X
Z
x = Bit is unknown
R/W-x
DC
DS40300C-page 19
R/W-x
C
bit 0
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