PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 145
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PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K22-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 000
Company:
Part Number:
PIC18F25K22-I/SO
Manufacturer:
MICROCHIP
Quantity:
7
Part Number:
PIC18F25K22-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 145 of 496
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TABLE 10-9:
TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC
2010 Microchip Technology Inc.
ANSELC
ECCP1AS
CCP1CON
ECCP2AS
CCP2CON
CTMUCONH
LATC
PORTC
RCSTA1
SLRCON
SSP1CON1
T1CON
T3CON
T3GCON
T5CON
TRISC
TXSTA1
Legend:
Note 1:
CONFIG3H
Legend:
Name
Name
— = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.
Available on PIC18(L)F4XK22 devices.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.
CCP1ASE
CCP2ASE
MCLRE
CTMUEN
TMR3GE
TRISC7
ANSC7
Bit 7
LATC7
WCOL
SPEN
CSRC
Bit 7
RC7
TMR1CS<1:0>
TMR3CS<1:0>
TMR5CS<1:0>
REGISTERS ASSOCIATED WITH PORTC
—
P1M<1:0>
P2M<1:0>
T3GPOL
SSPOV
TRISC6
ANSC6
Bit 6
LATC6
Bit 6
RC6
RX9
—
TX9
—
—
CCP2AS<2:0>
CCP1AS<2:0>
CTMUSIDL
P2BMX
TRISC5
ANSC5
SSPEN
T3GTM
Bit 5
LATC5
SREN
TXEN
Bit 5
RC5
T1CKPS<1:0>
T3CKPS<1:0>
T5CKPS<1:0>
—
DC1B<1:0>
DC2B<1:0>
T3CMX
T3GSPM T3GGO/DONE
Preliminary
SLRE
TRISC4
ANSC4
Bit 4
LATC4
TGEN
CREN
SYNC
Bit 4
RC4
CKP
(1)
T1SOSCEN
T3SOSCEN
HFOFST
T5OSCEN
EDGEN
SLRD
TRISC3
ADDEN
SENDB
ANSC3
Bit 3
LATC3
Bit 3
RC3
PIC18(L)F2X/4XK22
PSS1AC<1:0>
PSS2AC<1:0>
(1)
CCP3MX
Bit 2
EDGSEQEN
T1SYNC
T3SYNC
T5SYNC
T3GVAL
CCP1M<3:0>
CCP2M<3:0>
TRISC2
ANSC2
LATC2
SSPM<3:0>
BRGH
FERR
SLRC
Bit 2
RC2
PBADEN
Bit 1
IDISSEN
T1RD16 TMR1ON
T3RD16 TMR3ON
T5RD16 TMR5ON
TRISC1
LATC1
OERR
TRMT
SLRB
Bit 1
RC1
PSS1BD<1:0>
PSS2BD<1:0>
—
T3GSS
CCP2MX
Bit 0
DS41412D-page 145
CTTRIG
TRISC0
LATC0
RX9D
SLRA
TX9D
Bit 0
RC0
—
Register
on Page
Register
on Page
354
153
201
201
329
155
151
273
156
256
170
170
171
170
154
272
205
205
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