DSPIC30F6011A-30I/PT Microchip Technology Inc., DSPIC30F6011A-30I/PT Datasheet - Page 161

• Manufacturer Part Number: DSPIC30F6011A-30I/PT
• Description: DSP, 16-Bit, 132 KB Flash, 6KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6011A-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 2K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 132K Bytes
• Ram Size: 6K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR. The
Sleep status bit in RCON register is set upon wake-up.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
status bit. In a POR, the Sleep bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO status bits are both set.
20.7.2
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module
that allows them to operate during Idle.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• on any interrupt that is individually enabled (IE bit
• on any Reset (POR, BOR, MCLR)
• on WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins immedi-
ately, starting with the instruction following the PWRSAV
instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The IDLE status bit in
RCON register is set upon wake-up.
© 2006 Microchip Technology Inc.
Note:
is ‘1’) and meets the required priority level
In spite of various delays applied (T
T
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency crys-
tals). In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the clock failure trap,
the FRC oscillator will be enabled, and the
user will have to re-enable the crystal oscil-
lator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable, and will
remain in Sleep until the oscillator clock has
started.
IDLE MODE
LOCK
and T
dsPIC30F6011A/6012A/6013A/6014A
PWRT
), the crystal oscillator
POR
Preliminary
,
Any Reset, other than POR, will set the Idle status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
20.8
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are six device
Configuration registers available to the user:
1.
2.
3.
4.
5.
6.
The placement of the Configuration bits is automatically
handled when you select the device in your device pro-
grammer. The desired state of the Configuration bits may
be specified in the source code (dependent on the lan-
guage tool used), or through the programming interface.
After the device has been programmed, the application
software may read the Configuration bit values through
the table read instructions. For additional information,
please refer to the “dsPIC30F Flash Programming Spec-
ification” (DS70102) and the “dsPIC30F Family Refer-
ence Manual” (DS70046)..
Note:
FOSC (0xF80000): Oscillator Configuration
register
FWDT (0xF80002): Watchdog Timer
Configuration register
FBORPOR (0xF80004): BOR and POR
Configuration register
FBS (0xF80006): Boot Code Segment
Configuration register
FSS (0xF80008): Secure Code Segment
Configuration register
FGS (0xF8000A): General Code Segment
Configuration register
Device Configuration Registers
If the code protection Configuration Fuse
bits (FBS(BSS<2:0>), FSS(SSS<2:0>),
FGS<GSS>, FGS<GWRP>) have been
programmed, an erase of the entire code-
protected device is only possible at volt-
ages VDD
4.5V..
DS70143C-page 159