DSPIC30F6011A-30I/PT Microchip Technology Inc., DSPIC30F6011A-30I/PT Datasheet - Page 89

• Manufacturer Part Number: DSPIC30F6011A-30I/PT
• Description: DSP, 16-Bit, 132 KB Flash, 6KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6011A-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 2K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 132K Bytes
• Ram Size: 6K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.0
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring oper-
ational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
FIGURE 13-1:
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Timer Module
From General Purpose
Note:
OUTPUT COMPARE MODULE
TMR2<15:0
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
0
dsPIC30F6011A/6012A/6013A/6014A
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
1
OCTSEL
T2P2_MATCH
Preliminary
0
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These Operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC DSC devices contain up to
8 compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
T3P3_MATCH
Mode Select
OCM<2:0>
1
Output
3
Logic
Set Flag bit
OCxIF
R
S
Q
Output
Enable
(for x = 1, 2, 3 or 4)
(for x = 5, 6, 7 or 8)
or OCFB
OCFA
DS70143C-page 87
OCx