PIC16F873-04/SP Microchip Technology Inc., PIC16F873-04/SP Datasheet - Page 62

• Manufacturer Part Number: PIC16F873-04/SP
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F873-04/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87X
8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
8.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
DS30292C-page 60
RC2/CCP1
Note:
Special event trigger will:
pin
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC I/O
data latch.
CCP PIN CONFIGURATION
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
Output
Logic
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCP1IF
(PIR1<2>)
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
8.2.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note:
The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
2001 Microchip Technology Inc.