PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 25

• Manufacturer Part Number: PIC16F72-I/SO
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 3-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
FIGURE 3-3:
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
 2002 Microchip Technology Inc.
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
RBPU
Data
Bus
WR
Port
WR
TRIS
RB0/INT
(1)
and clear the RBPU bit (OPTION<7>).
PORTB and the TRISB Register
RD Port
Data Latch
TRIS Latch
RD TRIS
D
D
CK
CK
PORTB
PORTB
TRISB
0xCF
TRISB
Q
Q
Schmitt Trigger
Buffer
INITIALIZING PORTB
BLOCK DIAGRAM OF
RB3:RB0 PINS
; Select bank for PORTB
; Initialize PORTB by
; clearing output
; data latches
; Select Bank for TRISB
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Q
EN
D
TTL
Input
Buffer
V
RD Port
P
DD
Weak
Pull-up
V
V
DD
SS
I/O pin
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION<6>).
FIGURE 3-4:
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
Set RBIF
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
RBPU
Data
Bus
WR
Port
WR
TRIS
RB7:RB6 in Serial Programming Mode
From Other
RB7:RB4 Pins
and clear the RBPU bit (OPTION<7>).
(1)
RD TRIS
RD Port
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
Q
Q
Latch
PIC16F72
EN
EN
TTL
Input
Buffer
D
D
V
DS39597B-page 23
P
DD
Weak
Pull-up
RD Port
Q1
V
V
Q3
Buffer
DD
SS
ST
I/O pin