PIC16F871-I/PT Microchip Technology Inc., PIC16F871-I/PT Datasheet - Page 33

• Manufacturer Part Number: PIC16F871-I/PT
• Description: 44 PIN, 7 KB FLASH, 128 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F871-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 33
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF, or WR, to determine if the write had finished.
EXAMPLE 3-4:
3.7
The PIC16F870/871 devices do not automatically ver-
ify the value written during a write operation. Depend-
ing on the application, good programming practice may
dictate that the value written to memory be verified
against the original value. This should be used in appli-
cations where excessive writes can stress bits near the
specified endurance limits.
 2003 Microchip Technology Inc.
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BSF
BCF
Write Verify
STATUS, RP1
STATUS, RP0
ADDRL, W
EEADR
ADDRH, W
EEADRH
VALUEL, W
EEDATA
VALUEH, W
EEDATH
STATUS, RP0
EECON1, EEPGD ;Point to Program memory
EECON1, WREN
INTCON, GIE
0x55
EECON2
0xAA
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
FLASH PROGRAM WRITE
;
;Bank 2
;Write address
;of desired
;program memory
;location
;Write value to
;program at
;desired memory
;location
;Bank 3
;Enable writes
;Only disable interrupts
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
;EECON2
;Start write operation
;Two NOPs to allow micro
;to setup for write
;Only enable interrupts
;if using interrupts,
;otherwise discard
;Disable writes
3.8
There are conditions when the device may not want to
write to the EEPROM data memory or FLASH program
memory. To protect against these spurious write condi-
tions, various mechanisms have been built into the
PIC16F870/871 devices. On power-up, the WREN bit
is cleared and the Power-up Timer (if enabled)
prevents writes.
The write initiate sequence and the WREN bit together,
help prevent any accidental writes during brown-out,
power glitches, or firmware malfunction.
3.9
The PIC16F870/871 devices have two code protect
mechanisms, one bit for EEPROM data memory and
two bits for FLASH program memory. Data can be read
and written to the EEPROM data memory, regardless
of the state of the code protection bit, CPD. When code
protection is enabled and CPD cleared, external
access via ICSP is disabled, regardless of the state of
the program memory code protect bits. This prevents
the contents of EEPROM data memory from being read
out of the device.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F870/871
devices can always read the values in program mem-
ory, regardless of the state of the code protect bits.
However, the state of the code protect bits and the
WRT bit will have different effects on writing to program
memory. Table 4-1 shows the effect of the code protect
bits and the WRT bit on program memory.
Once code protection has been enabled for either
EEPROM data memory or FLASH program memory,
only a full erase of the entire device will disable code
protection.
Protection Against Spurious
Writes
Operation While Code Protected
PIC16F870/871
DS30569B-page 31