PIC16F871-I/PT Microchip Technology Inc., PIC16F871-I/PT Datasheet - Page 59

• Manufacturer Part Number: PIC16F871-I/PT
• Description: 44 PIN, 7 KB FLASH, 128 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F871-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 33
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
8.3.1
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
 2003 Microchip Technology Inc.
RC2/CCP1
Note:
Special event trigger will:
pin
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
Output
Logic
COMPARE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Set Flag bit CCP1IF
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
8.3.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.3.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.3.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair, and starts an A/D conversion (if A/D
module is enabled). This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Note:
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
PIC16F870/871
DS30569B-page 57