PIC16F737-I/SO Microchip Technology Inc., PIC16F737-I/SO Datasheet - Page 193

• Manufacturer Part Number: PIC16F737-I/SO
• Description: MCU, 8-Bit, 4KW Flash, 368 RAM, 25 I/O, SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SO

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.18.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
FIGURE 15-16:
 2004 Microchip Technology Inc.
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
OSC1
CLKO
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
Note 1:
2:
3:
4:
(4)
PC
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKO is not available in these oscillator modes but shown here for timing reference.
OST
WAKE-UP USING INTERRUPTS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
= 1024 T
Inst(PC – 1)
PC
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
(drawing not to scale). This delay will not be there for RC Oscillator mode.
Inst(PC + 1)
PC + 1
Sleep
Processor in
Sleep
PC + 2
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
PC + 2
Interrupt Latency
Dummy Cycle
(Note 2)
PC + 2
Dummy Cycle
PIC16F7X7
Inst(0004h)
0004h
DS30498C-page 191
Inst(0005h)
Inst(0004h)
0005h