PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 79
PIC16F872-I/SP
Manufacturer Part Number
PIC16F872-I/SP
Description
28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F872-ISP.pdf
(168 pages)
Specifications of PIC16F872-I/SP
A/d Inputs
5-Channel, 10-Bit
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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9.2.18.3
Bus collision occurs during a STOP condition if:
a)
b)
FIGURE 9-25:
FIGURE 9-26:
© 2006 Microchip Technology Inc.
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
SSPIF
BCLIF
SDA
SCL
PEN
BCLIF
P
SSPIF
SDA
PEN
SCL
P
Bus Collision During a STOP
Condition
'0'
'0'
'0'
'0'
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
T
BRG
T
BRG
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs. This
is a case of another master attempting to drive a data
'0' (Figure 9-25).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
PIC16F872
'0'
'0'
SDA sampled
low after T
set BCLIF
DS30221C-page 77
BRG
,
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