PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 251

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

23.4.2
The fail-safe condition is terminated by either a device
Reset or by entering a power managed mode. On Reset,
the controller starts the primary clock source specified in
Configuration Register 1H (with any required start-up
delays that are required for the oscillator mode, such as
OST or PLL timer). The INTOSC multiplexer provides the
system clock until the primary clock source becomes
ready (similar to a Two-speed Start-up). The clock system
source is then switched to the primary clock (indicated by
the OSTS bit in the OSCCON register becoming set). The
Fail-Safe Clock Monitor then resumes monitoring the
peripheral clock.
FIGURE 23-4:
 2003 Microchip Technology Inc.
Sample Clock
Note:
CM Output
OSCFIF
System
EXITING FAIL-SAFE OPERATION
Output
Clock
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
CM Test
PIC18F2220/2320/4220/4320
The primary clock source may never become ready dur-
ing start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain in
its Reset state until a power managed mode is entered.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the fail-safe condition. When the fail-safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
CM Test
Oscillator
Failure
Detected
Failure
CM Test
DS39599C-page 249