KSZ8721CL TR Micrel Inc, KSZ8721CL TR Datasheet - Page 30

TXRX 10/100 3.3V 48-LQFP

KSZ8721CL TR

Manufacturer Part Number
KSZ8721CL TR
Description
TXRX 10/100 3.3V 48-LQFP
Manufacturer
Micrel Inc
Type
Transceiverr
Datasheet

Specifications of KSZ8721CL TR

Number Of Drivers/receivers
1/1
Protocol
MII
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
KSZ8721CLTR
KSZ8721CLTR
KS8721CL
Symbol
t
Reference Circuit for Strapping Option Configuration
Figure 10 shows the reference circuit for strapping option pins.
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 11 when powering up the KS8721CL device. For
the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit
as shown in Figure 12.
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA
provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage.
At worst case, the both VDD core and VDDIO voltages should come up at the same time.
M9999-041405
sr
Parameter
Stable Supply Voltages to Reset High
Strap-In
Figure 12. Recommended Circuit for Interfacing with CPU/FPGA Reset
Voltage
RST_N
Supply
Value
KS8721CL
Figure 11. Recommended Reset Circuit.
Table 7. Reset Timing Parameters
RST
Figure 10. Reset Timing
KS8721CL
D1
D1: 1N4148
tsr
RST
10µF
VCC
C
30
D1
R
10k
D2
10µF
VCC
D1, D2: 1N4148
C
R
10k
RST_OUT_n
CPU/FPGA
Min
50
Typ
Max
Micrel, Inc.
April 2005
Units
µs

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