KSZ8721CL TR Micrel Inc, KSZ8721CL TR Datasheet - Page 9

• Manufacturer Part Number: KSZ8721CL TR
• Description: TXRX 10/100 3.3V 48-LQFP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721CL TR

• Number Of Drivers/receivers: 1/1
• Protocol: MII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KSZ8721CLTR; KSZ8721CLTR

Strapping Options
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
3. Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset. It is
April 2005
KS8721CL
Pin Number
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
recommended that an external pull-down via 1kΩ resistor be used in their applications to augment the 8721's internal pull-down.
11
21
22
6,5,
9
4,3
25
27
28
29
30
(3)
(3)
(3)
(3)
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
RMII_BTB
NWAYEN/
Pin Name
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED1
LED2
LED3
INT#
CRS
PD#
(1)
Type
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(2)
PU = Enable.
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
9
M9999-041405
Micrel, Inc.