IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 10

• Manufacturer Part Number: IDT82V2041EPP
• Description: IC LIU T1/J1/E1 1CH 44-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2041EPP

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82V2041EPP

Table-1 Pin Description (Continued)
Pin Description
IDT82V2041E
MODE1
MODE0
RCLKE
MCLK
Name
RCLK
LOS
REF
Type
O
O
I
I
I
I
Pin No.
43
17
16
11
4
9
7
RCLK: Receive Clock output
This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS condition with AIS enabled
(bit AISE=1), RCLK is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from the RTIP/
RRING signal. The receive data (RD in single rail mode or RDP and RDN in dual rail mode) is clocked out of the device on the
active edge of RCLK. If clock recovery is bypassed, RCLK is the exclusive OR (XOR) output of the dual rail slicer data RDP
and RDN. This signal can be used in applications with external clock recovery circuitry.
MCLK: Master Clock input
A built-in clock system that accepts selectable 2.048MHz reference for E1 operating mode and 1.544MHz reference for T1/J1
operating mode. This reference clock is used to generate several internal reference signals:
•
•
•
•
•
•
The loss of MCLK will turn TTIP/TRING into high impedance status.
LOS: Loss of Signal Output
This is an active high signal used to indicate the loss of received signal. When LOS pin becomes high, it indicates the loss of
received signal. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss
of signal are described in
REF: reference resister
An external resistor (3 KΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
MODE[1:0]: operation mode of Control interface select
The level on this pin determines which control mode is used to control the device as follows:
•
•
•
RCLKE: the active edge of RCLK select
In hardware control mode, this pin selects the active edge of RCLK
•
•
In software control mode, this pin should be connected to GNDIO.
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition.
Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband Loopback
code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as the reference
clock.
Reference clock during the Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode.
The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
The parallel multiplexed microcontroller interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and
INT pins. (refer to
Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, RPD, MODE[1:0]
and RXTXM[1:0]
L= select the rising edge as the active edge of RCLK
H= select the falling edge as the active edge of RCLK
MODE[1:0]
00
01
10
11
3.12 Microcontroller Interfaces
3.6 Los And AIS
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Hardware interface
Serial Microcontroller Interface
Parallel –Multiplexed -Motorola Interface
Parallel –Multiplexed -Intel Interface
10
Detection.
Control Interface mode
for details)
Description
December 9, 2005