MAX8520ETP Maxim Integrated Products, MAX8520ETP Datasheet - Page 15

• Manufacturer Part Number: MAX8520ETP
• Description: Other Power Management TEC Power Driver for Optical Modules
• Manufacturer: Maxim Integrated Products
• Type: TEC Power Driversr

Specifications of MAX8520ETP

• Input Voltage Range: 3 V to 5.5 V
• Input Current: 14 mA
• Power Dissipation: 1.67 W
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-20
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Take care not to exceed the positive or negative cur-
rent limit on the TEC. Refer to the manufacturer’s data
sheet for these limits.
Apply a voltage to the MAXV pin to control the maxi-
mum differential TEC voltage. V
to V
V
Set V
GND using resistors from 10kΩ to 100kΩ. V
vary from 0V to V
The voltage at CTLI directly sets the TEC current. CTLI
is typically driven from the output of a temperature con-
trol loop. The transfer function relating current through
the TEC (I
where V
ITEC = (V
CTLI is centered around REF (1.50V). I
CTLI = 1.50V. When V
OS2 to OS1. The voltages on the pins relate as follows:
The opposite applies when V
from OS1 to OS2:
The MAX8520/MAX8521 can be placed in a power-saving
shutdown mode by driving SHDN low. When the
MAX8520/MAX8521 are shut down, the TEC is off (OS1
and OS2 decay to GND) and supply current is reduced to
2mA (typ).
ITEC is a status output that provides a voltage proportional
to the actual TEC current. V
is zero. The transfer function for the ITEC output is:
Use ITEC to monitor the cooling or heating current
through the TEC. For stability keep the load capaci-
tance on ITEC to less than 150pF.
|V
MAXV
OS1
REF
MAXV
and can be positive or negative:
- V
REF
. The voltage across the TEC is four times
OS1
TEC
I
OS2
TEC
V
with a resistor-divider between REF and
is 1.50V and:
ITEC
) and V
| = 4 x V
- V
= (V
CS
REF
= 1.50V + 8
V
V
______________________________________________________________________________________
CTLI
)/R
OS2
OS2
.
Smallest TEC Power Drivers for Optical
CTLI
CTLI
MAXV
SENSE
Setting Max TEC Voltage
> V
< V
- V
is given by:
> 1.50V the current flow is from
ITEC
Control Inputs/Outputs
REF
OS1
OS1
or V
CTLI

)/(10
Output Current Control
= V
> V
< V
(V
DD
MAXV
OS1
< 1.50V current flows
REF
, whichever is lower
CS
CS

Shutdown Control
R
– V
can vary from 0V
when TEC current
TEC
SENSE
CS
ITEC Output
is zero when
)
)
MAXV
can
The MAX8520/MAX8521 typically drive a thermo-elec-
tric cooler inside a thermal-control loop. TEC drive
polarity and power are regulated based on temperature
information read from a thermistor or other temperature-
measuring device to maintain a stable control tempera-
ture. Temperature stability of +0.01°C can be achieved
with carefully selected external components.
There are numerous ways to implement the thermal loop.
Figures 1 and 2 show designs that employ precision op
amps, along with a DAC or potentiometer to set the con-
trol temperature. The loop can also be implemented digi-
tally, using a precision A/D to read the thermistor or other
temperature sensor, a microcontroller to implement the
control algorithm, and a DAC (or filtered-PWM signal) to
send the appropriate signal to the MAX8520/MAX8521
CTLI input. Regardless of the form taken by the thermal-
control circuitry, all designs are similar in that they read
temperature, compare it to a set-point signal, and then
send an error-correcting signal to the MAX8520/
MAX8521 that moves the temperature in the appropriate
direction.
High switching frequencies and large peak currents
make PCB layout a very important part of design. Good
design minimizes excessive EMI and voltage gradients
in the ground plane, both of which can result in instabil-
ity or regulation errors. Follow these guidelines for good
PCB layout:
1) Place decoupling capacitors as close to the IC pins
as possible.
2) Keep a separate power ground plane, which is con-
nected to PGND1 and PGND2. PVDD1, PVDD2,
PGND1 and PGND2 are noisy points. Connect decou-
pling capacitors from PVDD_ to PGND_ as direct as
possible. Output capacitors C2, C7 returns are con-
nected to PGND plane.
3) Connect a decoupling capacitor from V
Connect GND to a signal ground plane (separate from
the power ground plane above). Other V
capacitors (such as the input capacitor) need to be
connected to the PGND plane.
4) Connect GND and PGND_ pins together at a single
point, as close as possible to the chip.
5) Keep the power loop, which consists of input capaci-
tors, output inductors and capacitors, as compact and
small as possible.
Applications Information
PCB Layout and Routing
Modules
DD
DD
decoupling
to GND.
15