MAX8520ETP Maxim Integrated Products, MAX8520ETP Datasheet - Page 16
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MAX8520ETP
Manufacturer Part Number
MAX8520ETP
Description
Other Power Management TEC Power Driver for Optical Modules
Manufacturer
Maxim Integrated Products
Type
TEC Power Driversr
Datasheet
1.MAX8521ETP.pdf
(18 pages)
Specifications of MAX8520ETP
Input Voltage Range
3 V to 5.5 V
Input Current
14 mA
Power Dissipation
1.67 W
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
TQFN-20
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX8520ETP
Manufacturer:
MAXIM/美信
Quantity:
20 000
Company:
Part Number:
MAX8520ETP+
Manufacturer:
Maxim Integrated Products
Quantity:
419
Company:
Part Number:
MAX8520ETP+T
Manufacturer:
MAXIM
Quantity:
6
Part Number:
MAX8520ETP+T
Manufacturer:
MAXIM/美信
Quantity:
20 000
6) To ensure high DC-loop gain and minimum loop
error, keep the board layout adjacent to the negative
input pin of the integrator (U2 in Figure1) clean and free
of moisture. Any contamination or leakage current into
this node can act to lower the DC gain of the integrator
which can degrade the accuracy of the thermal loop. If
space is available, it can also be helpful to surround the
negative input node of the integrator with a grounded
guard ring.
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
Smallest TEC Power Drivers for Optical
Modules
16
______________________________________________________________________________________
TOP VIEW
CONNECT EP TO GND
PACKAGE TYPE
20 TQFN-EP
6 x 6 UCSP
PGND1
36 WLP
COMP
SHDN
ITEC
LX1
1
2
3
4
5
+
MAX8520/
MAX8521
TQFN
EP
PACKAGE CODE
W363A3+2
15
14
13
12
11
T2055+4
B36-2
LX2
PGND2
FREQ
V
GND
DD
Refer to the MAX8520/MAX8521 evaluation kit for a
PCB layout example.
PROCESS: BiCMOS
BUMPS ON BOTTOM
OUTLINE NO.
TOP VIEW
21-0140
21-0082
21-0024
PGND2 PGND2 PGND2 PGND1 PGND1 PGND1
PVDD2
VDD
GND
OS2
LX2
E6
D6
C6
B6
A6
F6
PVDD2
GND2
FREQ
CTLI
LX2
Package Information
E5
D5
C5
B5
A5
F5
Pin Configurations
Refer to
Refer to
UCSP/WLP
GND2
REF
D4
C4
A4
F4
CS
Chip Information
MAX8521
GND2
MAXV
OS1
D3
C3
A3
F3
PATTERN NO.
Application Note 1891
Application Note 1891
90-0009
LAND
PVDD1 PVDD1
COMP SHDN
MAXIP MAXIN
GND2
LX1
D2
C2
F2
E2
B2
A2
ITEC
LX1
D1
C1
F1
E1
B1
A1
+