MAX1586AETM Maxim Integrated Products, MAX1586AETM Datasheet - Page 23

• Manufacturer Part Number: MAX1586AETM
• Description: Other Power Management PMICs w/Dynamic Core for PDAs
• Manufacturer: Maxim Integrated Products

The serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). Standard I
write-byte commands are used. Figure 5 shows a tim-
ing diagram for the I
MAX1587 are slave-only devices, relying upon a master
to generate a clock signal. The master (typically a
microprocessor) initiates data transfer on the bus and
generates SCL to permit data transfer. A master device
communicates to the MAX1586/MAX1587 by transmit-
ting the proper address followed by the 8-bit data code
(Table 2). Each transmit sequence is framed by a
START (A) condition and a STOP (L) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
Table 2 shows the serial data codes used to program
V3 and V6. The default power-up voltage for V3 is 1.3V
and for V6 is 0V.
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the bus is not busy.
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 5). A START condition from the master signals
the beginning of a transmission to the MAX1586/
MAX1587. The master terminates transmission by issu-
ing a not acknowledge followed by a STOP condition
Figure 5. I
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMB DATA LINE LOW
SCL
SDA
2
t
SU:STA
C-Compatible Serial-Interface Timing Diagram
Dynamic Core for PDAs and Smart Phones
A
t
HD:STA
______________________________________________________________________________________
START and STOP Conditions
t
LOW
2
B
C protocol. The MAX1586/
t
HIGH
High-Efficiency, Low-I
t
SU:DAT
C
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMB DATA LINE LOW
Bit Transfer
2
C-compatible
D
E
F
(see the Acknowledge Bit (ACK) section). The STOP
condition frees the bus.
When a STOP condition or incorrect address is detect-
ed, the MAX1586/MAX1587 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.
The acknowledge bit (ACK) is the ninth bit attached to
every 8-bit data word. The receiving device always
generates ACK. The MAX1586/MAX1587 generate an
ACK when receiving an address or data by pulling SDA
low during the ninth clock period. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Table 3). When idle, the
MAX1586/MAX1587 wait for a START condition fol-
lowed by its slave address. The serial interface com-
pares each address value bit by bit, allowing the
interface to power down immediately if an incorrect
address is detected.
Table 3. Serial Address
SRAD
t
HD:DAT
0
1
G
A7
0
0
A6
0
0
H
A5
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
1
1
Q
I
A4
0
0
PMICs with
J
Acknowledge Bit (ACK)
A3
1
1
K
A2
0
0
Serial Address
t
SU:STO
A1
0
1
L
t
BUF
M
RD/W
A0
0
0
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