ISPPAC-POWR604-01T44I Lattice, ISPPAC-POWR604-01T44I Datasheet - Page 21

• Manufacturer Part Number: ISPPAC-POWR604-01T44I
• Description: Supervisory Circuits 5V 8 Macro Cell
• Manufacturer: Lattice

Specifications of ISPPAC-POWR604-01T44I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ADDCFG – This instruction is used to set the address of the CFG array for subsequent program or read operations.
This instruction also forces the outputs into the SAFESTATE.
DATACFG – This instruction is used to shift data into the CFG register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASECFG – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
PROGCFG – This instruction programs the selected CFG array column. This specific column is preselected by
using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG
state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces
the outputs into the SAFESTATE.
READCFG – This instruction is used to read the content of the selected CFG array column. This specific column is
preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE.
CFGBE – This instruction will bulk erase all E
The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the out-
puts into the SAFESTATE.
SAFESTATE – This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET
drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG
state.
PROGRAMEN – This instruction enables the programming mode of the ispPAC-POWR604. This instruction also
forces the outputs into the SAFESTATE.
IDCODE – This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 10), to support reading out the identification code.
Figure 10. IDCODE Register
PROGRAMDIS – This instruction disables the programming mode of the ispPAC-POWR604. The Test-Logic-Reset
JTAG state can also be used to cancel the programming mode of the ispPAC-POWR604.
ADDSTATUS – This instruction is used to both connect the status register to TDO (Figure 11) and latch the 6 volt-
age monitor (comparator outputs) into the status register. Latching of the 6 comparator outputs into the status reg-
ister occurs during Capture-Data-Register JTAG state.
Figure 11. Status Register
ERASEUES – This instruction will bulk erase the content of the UES E
be in programming mode (PROGRAMEN instruction) and operated. This instruction also forces the outputs into the
SAFESTATE.
SHIFTUES – This instruction both reads the E
between the TDI and TDO pins (as shown in Figure U), to support programming or reading of the user electronic
signature bits.
Bit
31
Bit
30
Bit
29
VMON
Bit
28
1
VMON
Bit
27
2
2
VMON
CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-POWR604.
2
3
CMOS bits into the UES register and places the UES register
VMON
21
4
VMON
Bit
4
5
VMON
2
CMOS memory. The device must already
Bit
3
6
ispPAC-POWR604 Data Sheet
TDO
Bit
2
Bit
1
Bit
0
TDO