ISPPAC-POWR604-01T44I Lattice, ISPPAC-POWR604-01T44I Datasheet - Page 25

• Manufacturer Part Number: ISPPAC-POWR604-01T44I
• Description: Supervisory Circuits 5V 8 Macro Cell
• Manufacturer: Lattice

Specifications of ISPPAC-POWR604-01T44I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the
four internal programmable timers used for sequence delay.
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User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E
CMOS.
Figure 15. PAC-Designer LogiBuilder Screen
Programming of the ispPAC-POWR604 is accomplished using the Lattice ispDOWNLOAD Cable. This cable con-
nects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the JTAG
TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that
the user has defined during the design process.
Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been com-
pleted, the power supply to the ispPAC-POWR604 can be set from 2.25V to 5V. Once programmed, the on-chip
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non-volatile E
CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip points
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for comparators etc. Upon powering the device up, the non-volatile E
CMOS bits control the device configuration. If
design changes need to be made such as adjusting comparator trip points or changes to the digital logic functions,
the device is simply re-programmed using the ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulation of the control sequence is provided using the design tools Waveform Editor and
Waveform Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simula-
tion engine combines the design file with a stimulus file (edited by the user with the Waveform Editor) to produce an
output file that can be observed with the Waveform Viewer (Figure 16).
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