EL9112ILZ-T7 Intersil, EL9112ILZ-T7 Datasheet - Page 11
![IC DIFF RCVR/EQUALZR TRPL 28-QFN](/photos/28/19/281933/28-vqfn_l28_sml.jpg)
EL9112ILZ-T7
Manufacturer Part Number
EL9112ILZ-T7
Description
IC DIFF RCVR/EQUALZR TRPL 28-QFN
Manufacturer
Intersil
Type
Receiverr
Datasheet
1.EL9111ILZ.pdf
(13 pages)
Specifications of EL9112ILZ-T7
Number Of Drivers/receivers
0/3
Protocol
Twisted-Pair
Voltage - Supply
5V
Mounting Type
Surface Mount
Package / Case
28-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Decoding is based on the EL4543 encoding scheme, as
described in Figure 27 and Table 1. The scheme is a three-
level system, which has been designed such that the sum of
the common mode voltages results in a fixed average DC
level with no AC content. This eliminates the effect of EMI
radiation into the common mode signals along the twisted
pairs of the cable.
The common mode voltages are initially extracted by the
EL9111 from the three input pairs. These are then passed to
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (H
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
RED CM
High
Low
Mid
Mid
FIGURE 27. H AND V SYNCS ENCODED
TABLE 1. H AND V SYNC DECODING
GREEN CM
High
High
Low
Low
TIME (0.5ms/DIV)
BLUE CM
11
High
Low
Mid
Mid
OUT
and V
H
OUT
High
High
Low
Low
SYNC
).
BLUE CM
OUT (CH A)
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
V
H
SYNC
V
SYNC
High
High
SYNC
Low
Low
EL9111, EL9112
Sync Ref
The Sync Ref pin is the reference level for the logic low of the
sync outputs. It can be tied to 0V or -5V, but for typical
operation, the Sync Ref pin would tie to 0V. The Sync output
logic low level approaches Sync Ref within V
high will approach V
with a 10V single supply and Sync Ref at ground will cause the
HOUT and VOUT pins to go from ground to V
This is too large a voltage for logic inputs, so an output voltage
divider of 1kΩ series from the outputs with 1kΩ to ground will
reduce the output logic levels to 0V and 5V. Different logic
levels may require different output divider ratios.
The Sync Ref is intended to sink all the switching currents as
transitions to logic low are made. This prevents switching
signals crosstalk to the main chip 0V line, as well as adding the
flexibility of referencing to -5V. Thus, the logic output buffer
does use Sync Ref as its negative supply. The Sync Ref pin is
connected to the analog -5V or analog ground as needed and
is a separate pin to prevent noise coupling in the chip.
EL9111 with Single Ended Coax Input
The EL9111 is designed to use twisted pair cat 5 cable input
with sync encoded as differential CMV on the RGB pairs.
Coax cable inputs may be used with a few changes and
limitations. Coax cable cannot have sync encoded as CMV,
so the coax shields are grounded along with the EL9111
RGB minus inputs. The coax center conductor is terminated
with 75Ω and connected to the RGB plus inputs. The result
is half the video signal will be seen as CMV by the sync
decoding circuit that decodes the video as sync. This causes
noise on the RGB outputs. The noise may be eliminated by
connecting the Sync Ref pin to V
Outputs which now typically go to about 3V with +5
SP
within V
CESAT
SP
. The EL9111 operating
to disable the Sync
CESAT
SP
, a 10V swing.
; the logic
V
May 9, 2007
SP
FN7450.4
.