PSB21150FV14XP Lantiq, PSB21150FV14XP Datasheet - Page 11
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PSB21150FV14XP
Manufacturer Part Number
PSB21150FV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PSB21150FV14XP.pdf
(270 pages)
Specifications of PSB21150FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
- Current page: 11 of 270
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List of Figures
Figure 76
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Data Sheet
Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . 136
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Data Reception Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 161
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Register Mapping of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 241
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 243
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 244
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Sampling Time in LT-S/NT Mode (M-Bit Input) . . . . . . . . . . . . . . . . . 250
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
11
PSB/PSF 21150
2003-01-30
IPAC-X
Page
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