MC145572EI Freescale Semiconductor, MC145572EI Datasheet - Page 169
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MC145572EI
Manufacturer Part Number
MC145572EI
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC145572EI.pdf
(264 pages)
Specifications of MC145572EI
Number Of Line Interfaces
1
Control Interface
HDLC
Package Type
PLCC
Lead Free Status / Rohs Status
Compliant
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MOTOROLA
10.7.3
FSX OR
TSEN
D out
FSR
DCL
D in
28
IDL2 Master Long Frame Sync, 8- and 10-Bit Formats
NOTES:
Ref. No.
Figure 10–3. Long Frame Sync Master Timing, 8– and 10–Bit Formats
1. FSR or FSX occurs on average every 125 s.
2. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for
3. In IDL Master Long Frame Sync mode, the FSR or FSX pulse is eight DCL clock periods long.
4. The DCL frequency may be 512 kHz, 2.048 MHz, or 2.56 MHz.
5. In IDL 8– and 10–bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
27
28
29
30
31
32
33
34
35
36
37
38
39
all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the
received signal when operating in NT mode. This timing adjustment does not occur during the 2B+D data transfer. The tim-
ing adjustment is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL clock
on two successive IDL frames, once per U–Interface basic frame. The total adjustment is 96 ns distributed over the two
IDL frames.
1
38
30
FSR or FSX Period
Delay From Rising Edge of DCL to Rising Edge of FSR or FSX
Delay From Rising Edge of DCL to Falling Edge of FSR or FSX
Delay From Rising Edge of FSR to Low–Z and Valid Data on
D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL to High–Z on D out
DCL Clock Period
DCL Pulse Width High
DCL Pulse Width Low
Data Valid on D in Before Falling Edge of DCL (D in Setup Time)
Data Valid on D in After Falling Edge of DCL (D in Hold Time)
Delay From Rising Edge of FSR to TSEN Low
Delay From Falling Edge of DCL to TSEN High
2
Freescale Semiconductor, Inc.
For More Information On This Product,
3
36
4
Go to: www.freescale.com
Parameter
34
5
MC145572
35
37
6
27
7
33
31
8
9
39
Min
125
391
—
—
—
—
45
45
25
25
—
—
5
29
1953
Max
32
30
30
30
30
30
55
55
30
30
—
—
—
% of DCL
% of DCL
Period
Period
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
10–7
1
2
3
4
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