PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 66
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PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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3.4
Figure 34
7.68 MHz clock signal (f
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
An internal clock divider provides an FSC (ACFG2.FBS=0) or BCL (ACFG2.FBS=1)
output on pin AUX5/FBOUT derived from the DCL clock. The output can be enabled via
ACFG2.A5SEL=1.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see
Figure 34
Data Sheet
XTAL
7.68 MHz
shows the clock system of the ISAC-SX. The oscillator is used to generate a
Clock Generation
OSC
Clock System of the ISAC-SX
f
XTAL
XTAL
DPLL
). In TE mode the DPLL generates the IOM-2 clocks FSC
Figure
Reset
Generation
SW Reset
C/I
EAW
Watchdog
ACFG2.FBS
66
3.2.4).
ACFG2.A5SEL
Description of Functional Blocks
FSC (TE mode)
DCL (TE mode)
BCL (TE mode)
SCLK (LT-T mode)
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
FBOUT (FSC/BCL output)
PEB 3086
2003-01-30
ISAC-SX
21150_06
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