PEB3081HV14XP Lantiq, PEB3081HV14XP Datasheet - Page 159
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PEB3081HV14XP
Manufacturer Part Number
PEB3081HV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3081HV14XP.pdf
(198 pages)
Specifications of PEB3081HV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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PEB 3081
PEF 3081
Detailed Register Description
Preliminary
EN_BCL ... Enable Bit Clock BCL/SCLK
0: The BCL/SCLK clock is disabled
1: The BCL/SCLK clock is enabled.
CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) or in NT, LT-S and Int. NT mode the DCL
from the IOM-2 interface is an input.
0: A double bit clock is connected to DCL
1: A single bit clock is connected to DCL
For general information please refer to
Chapter
3.7.
DIS_OD ... Disable Open Drain Drivers
0: DU/DD are open drain drivers
1: DU/DD are push pull drivers
DIS_IOM ... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection. However, the SBCX-X internal operation is independent of the DIS_IOM bit.
0: The IOM interface is enabled
1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance;
clock inputs are active; DU, DD data line inputs are switched off and outputs have high
impedance; except in TE/LT-T mode the DU line is input (“0”-level causes activation), so
the DU pin must be terminated (pull up resistor).
Data Sheet
159
2000-09-27
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