SP000007490 Infineon Technologies, SP000007490 Datasheet - Page 38
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SP000007490
Manufacturer Part Number
SP000007490
Description
Manufacturer
Infineon Technologies
Datasheet
1.SP000007490.pdf
(52 pages)
Specifications of SP000007490
Number Of Line Interfaces
1
Lead Free Status / Rohs Status
Compliant
4
Attention: Any warranty, whether express or implied shall be subject to the use of
4.1
The reset is activated by setting pin RES to low. The following functions are reset:
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•
•
•
•
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All settings are maintained until RES is high and the digital interface is synchronized.
Note: The system must not activate the IEC-4-AFE-X Version 3.2 for at least 20 µs after
4.2
When applying power to the IEC-4-AFE-X Version 3.2 an internal power-on-reset is
generated to reset the PLL/oscillator and to set CL15 to an input. If a 15.36 MHz clock is
generated by the internal PLL/oscillator or if an external clock is provided at XIN then
CL15 becomes an output and issues this clock.
If the supply voltage starts from a VDD voltage below 1.0V the IEC-4-AFE-X Version 3.2
guarantees proper POR function with the restriction that the rising V
minor 5V/4 µs.
The POR function is enabled again if the supply voltage V
minimum period of 80 ns (see figure
Note: The RES pin must be at "1" level during POR to enable the reset of the PLL/
Data Sheet
The reset activates the power down of all line ports.
The data on SDX is ignored during reset.
SDR is set to low
The range and the loop functions of all line ports are deactivated
On a falling edge at the RES pin, the PLL is reset to its nominal frequency and starts
to resynchronize after 130 ns.
Note: A running 15.36 MHz CL15 clock is required for this function.
The SCI
The digital low pass filter
rising edge on RES.
oscillator.
Operational Description
the chips within the procedure as outlined in the respective Data Sheet.
In case the chips are used incorrectly or not used within the logic or
electrical specifications, any and all warranty or other claim based on
any defect or malfunction whatsoever shall be excluded.
Reset
Power-on-Reset (POR)
Figure 11
38
and table
Table
DD
Operational Description
drops below 1.0 V for a
16).
DD
Rev. 1, 2004-05-28
slope has to be
PEB 24902
PEF 24902